Linux Versal EDAC Driver

Table of Contents

Overview

This documents provides driver details about the Xilinx DDR ECC controller driver used in Versal SOC.

Supporting Features

Xilinx Versal DDR ECC Controller supports

  • Single bit error detection and correction

  • Double bit error detection.

  • Interrupt support.

  • Error injection support for both single bit and double bit errors.

Missing features, Known Issues and Limitations

  • In 2020.2, we are not supporting the DTG flow to generate final dt node for EDAC.

Kernel Configurations

The following kernel configuration options should be enabled for compiling the Xilinx Versal EDAC driver.

  • CONFIG_EDAC=y

  • CONFIG_EDAC_XILINX_DDR=y

Enable the "EDAC Debug" configuration under CONFIG_EDAC - This is required for error injection support.

  • CONFIG_EDAC_DEBUG=y

Device tree Node

1 2 3 4 5 6 7 8 9 memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "okay"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupt-parent = <0x5>; interrupts = <0 0x93 4>; xlnx,mc-id = <0x0>; };

Requirements

  • DDRMC with ECC enabled design

Mainline Status

  • Not in mainline.

Test Procedure

DT changes:

  • For 2020.2 release we are not supporting DTG flow, so user must enable the memory controller node in the DTS file based on the design.

  • in DTS file, whichever DDRMC controller(>=1) is enabled (DDRMC0-DDRMC4), change the status variable from "disabled" to "okay" in memory-controller node.

Kernel Boot log for EDAC driver

1 2 3 4 5 6 root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# dmesg | grep "edac" [    1.648412] EDAC DEBUG: edac_mc_sysfs_init: device mc created [    2.702865] EDAC DEBUG: edac_mc_alloc: allocating 2392 bytes for mci data (1 ranks, 1 csrows/channels) [    2.702912] EDAC DEBUG: edac_mc_add_mc_with_groups: [    2.702945] EDAC DEBUG: edac_create_sysfs_mci_device: device mc0 created [    2.702975] EDAC MC0: Giving out device to module xlnx_edac controller xlnx_ddr_controller: DEV f6150000.memory-controller (INTERRUPT)

 

Test logs for CE and UE errors injection:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CE: ------------------------------------------------------------ root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# echo "CE" > /sys/devices/system/edac/mc/mc0/inject_data_poison root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# echo 0x2002000 > /sys/devices/system/edac/mc/mc0/inject_data_error root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# devmem 0x2002000 32 0x12345 root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# devmem 0x2002000 [ 42.107362] EDAC MC0: 1 CE Error type:CE MC ID: 0 Addr at 2002000 Burst Pos: 0 [ 42.107362] on unknown memory (csrow:0 channel:0 page:0x0 offset:0x0 grain:1 syndrome:0x0) 0x00012345 UE: ------------------------------------------------------------- root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# echo "UE" > /sys/devices/system/edac/mc/mc0/inject_data_poison root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# echo 0x2622000 > /sys/devices/system/edac/mc/mc0/inject_data_error root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# devmem 0x2622000 32 0x123 eroot@xilinx-vc-p-a2197-00-reva-x-prc-01:~# devmem 0x2622000 [ 66.763320] EDAC MC0: 1 UE Error type:UE MC ID: 0 Addr at 2622000 Burst Pos: 0 [ 66.763320] on unknown memory (csrow:0 channel:0 page:0x0 offset:0x0 grain:1) Bus error root@xilinx-vc-p-a2197-00-reva-x-prc-01:~#

Change log

2020.2

2021.1

  • d2aa9a9 - Fix the error path

  • 734c865 - Add support for registering for notification

  • d5a09f3 - enable the UE interrupt in IRQ1

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