SATA

Table Of Contents

Introduction

Serial ATA or SATA was designed to replace the old parallel ATA (or IDE) interface used mainly for storage devices. SATA uses the same ATA/ATAPI command-set,

but uses serial communication over 2 wire pairs at rates of 1.5, 3.0, and 6.0Gbit/sec. Serial data is 8b/10b encoded.

HW IP Features

  • SATA host controller supports 2 ports
  • Compliant with SATA 3.1 specs
  • Compliant with Advanced Host Controller Interface (AHCI) ver. 1.3
  • Supports 1.5, 3.0 and 6.0 Gbps data rates
  • 64-bit AXI master port with built-in DMA
  • 40/44 bit address space support
  • AHB/APB port for register programming
  • Supports Power management features like ‘partial’ and ‘slumber’ modes

Missing Features, Known Issues and Limitations

  • Doesn't support Devslp feature

Kernel Configuration

These below settings are to be set for enabling SATA support in Linux

Devicetree

Link

NEW Flow:

Performance


The performance is noted by connecting SATA drive to ZCU102 board using hdparm tool. Use petalinux apps setup and edit makefile to install app into rootfs.
The hdparm tool can be downloaded from this link - http://sourceforge.net/projects/hdparm/

Timing buffered disk read = 456MB/sec
Note : Above results may vary from device to device

Test Procedure


Re-scan for devices from command line

echo "- - -" > /sys/class/scsi_host/host1/scan

Sanity Testing

Expected O/P

Mainline status

The SATA driver is upstreamed into the mainline 5.4 kernel.

Phy Settings

The SATA Host Controller provides SATA connectivity for 1-2 external ports using the PS internal GT as PHY

Change Log

2016.3
  • None

2016.4
  • None

2017.1
Summary:
  • Added CCI support in SATA if "dma-coherent" flag is enabled in device-tree node
  • Corrected the sequence of AXI bus configuration register programming
  • Added Common Clock Framework for SATA
Commits:
1815f
69dcb

2017.2
  • None

2017.3
Summary:
  • Corrected suspend/resume logic for SATA
  • Added SMMU support for SATA IP
Commits:
a8e3b
398aa

2017.4
  • None

2018.1
Summary:
  • Merged 4.14 mainline kernel
Commits:

2018.2
Summary:
  • None


2018.3
Summary:
  • None


2019.1
Summary:
  • None

2019.2
Summary:

  • None

2020.1
Summary:

  • None

2020.2
Summary:

  • None

2021.1
Summary:

Summary:
  • Update the driver to support xilinx GT phy based on new flow GT driver
  •  Updated code by using dev_err_probe

Note: The new flow of psgtr applicable from release Xilinx - 2021.1.

Commits: