Introduction

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD2014B interface supporting line rates from 1Gbps to 12.5Gbps.
JESD204 can be configured as a transmitter or a reciever.

HW IP Features

Supports up to 8 lanes per core and up to 32 lanes using multiple cores
Supports Initial Lane Alignment
Supports scrambling
Supports 1–256 octets per frame
Supports 1–32 frames per multiframe
Supports Subclass 0, 1, and 2

Known Issues and Limitations

The driver is no longer maintained in the xilinx releases.

Kernel Configuration Options for Driver

To enable GPIO in the kernel, the following configuration options need to be enabled:

CONFIG_XILINX_JESD204B=y
CONFIG_XILINX_JESD204B_PHY=y

Devicetree

        jesd_Tx_axi_0: jesd_Tx@44a20000 {
            compatible = "xlnx,jesd204-5.1";
            reg = <0x44a20000 0x10000>;
                        xlnx,frames-per-multiframe = <30>;
                        xlnx,bytes-per-frame = <2>;
                        xlnx,subclass = <1>;
            xlnx,lanes = <0x2>;
            xlnx,node-is-transmit;
        } ;
        jesd_Rx_axi_0: jesd_Rx@44a00000 {
            compatible = "xlnx,jesd204-5.1";
            reg = <0x44a00000 0x10000>;
                        xlnx,frames-per-multiframe = <30>;
                        xlnx,bytes-per-frame = <2>;
                        xlnx,subclass = <1>;
            xlnx,lanes = <0x2>;
        } ;

Test procedure on Microblaze

# cat /sys/devices/axi@0/44a00000.jesd_Rx/lane0_info
DID: 0, BID: 0, LID: 0, L: 1, SCR: 0, F: 1
K: 1, M: 1, N: 1, CS: 0, S: 1, N': 1, HD: 0
FCHK: 0x0, CF: 0
ADJCNT: 0, PHYADJ: 0, ADJDIR: 0, JESDV: 0, SUBCLASS: 0
MFCNT : 0x0
ILACNT: 0x0
ERRCNT: 0x0
BUFCNT: 0x0
LECNT: 0x0
FC: 10

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