Table of Contents


The Xilinx® LogiCORE™ IP JESD204 core implements a JESD2014B interface supporting line rates from 1Gbps to 12.5Gbps.
JESD204 can be configured as a transmitter or a reciever.

HW IP Features

  • Supports up to 8 lanes per core and up to 32 lanes using multiple cores
  • Supports Initial Lane Alignment
  • Supports scrambling
  • Supports 1–256 octets per frame
  • Supports 1–32 frames per multiframe
  • Supports Subclass 0, 1, and 2

Known Issues and Limitations

  • None

Kernel Configuration Options for Driver

To enable GPIO in the kernel, the following configuration options need to be enabled:


Test procedure on Microblaze

Expected Output

Mainline Status

The driver is not mainlined.

Change Log

  • 2021.1
    • None

Related Links