Table of Contents
OverviewThis documents provides driver details about the Synopsys DDR ECC controller driver used in Zynq and ZynqMP SOC.
Zynq DDRC controller and ZynqMP SOC DDRC Controller supports single bit error correction and double bit error detection
ZynqMP DDRC controller has interrupt support and error injection support.
Zynq DDRC controller reports the single and double bit errors based on poll method.
ZynqMP DDRC controller reports the single and double bit errors based on interrupt method.
Missing features, Known Issues and Limitations
Kernel ConfigurationsThe following kernel configuration options should be enabled for compiling the Synopsys EDAC driver
CONFIG_EDAC_SYNOPSYS = y
Device tree Node Settings
Refer the device tree bindings doc.Documentation/devicetree/bindings/memory-controllers/synopsys.txtFor ZynqMP SOC device tree bindings docrefer devicetree bindings doc
For Zynq SOC
For ZynqMP SOC
This driver is in mainline.
Fixes related to coverity warning are not yet in mainline (~3 lines).
To test the EDAC driver on Zynq platform manually, below are the changes required in FSBL and U-Boot source:
Use the above changes in FSBL and U-Boot and compile Images.
Use the compiled FSBL and U-Boot Images while booting linux.
Now after booting Linux:
- Do not use symbolic permissions
- Fix for incorrect Macro defines
- Add Memory mapping, 16bit row mode and video buffer mode support
- Fixed incompatible parameter error
- Added more descriptive debug message
- Moved the CE bit information to main error message
- Fix the wrong value assignment for edac_mode.