SD controller

Introduction

Zynq

The SD/SDIO controller is compatible with the standard SD Host Controller Specification Version 2.0 Part A2 with SDMA (single operation DMA), ADMA1 (4 KB boundary limited DMA), and ADMA2 (ADMA2 allows data of any location and any size to be transferred in a 32-bit system memory - scatter-gather DMA) support. The core also supports up to seven functions in SD1, SD4, but does not support SPI mode. It does support SD high-speed (SDHS) and SD High Capacity (SDHC) card standards.

Zynqmp/Versal

The “Arasan SD3.0 / SDIO3.0 / eMMC4.51 Host Controller”(3MCR Host Controller) is a Host Controller with a AHB/AXI/OCP processor interface. This product conforms to SD Host Controller Standard Specification Version 3.00.
The 3MCR Host Controller handles SDIO/SD Protocol at transmission level, packing data, adding cyclic redundancy check (CRC), Start/End bit, and checking for transaction format correctness.
The 3MCR Host Controller provides Programmed IO method and DMA data transfer method. In programmed IO method, the Host processor transfers data using the Buffer Data Port Register. Host controller support for DMA can be determined by checking the DMA support in the Capabilities register. DMA allows a peripheral to read or write memory without the intervention from the CPU. The 3MCR Host Controller’s Host Controller system address register points to the first data address, and data is then accessed sequentially from that address.

HW/IP features

Zynq

The two SDIO controllers are controlled and operate independently with the same feature set:
Host mode controller
  • Four I/O signals (MIO or EMIO)
  • Command, Clock, CD, WP, Pwr Ctrl (MIO or EMIO)
  • LED control, bus voltage (EMIO)
  • Interrupt or polling driven
  • AHB master-slave interface operating at the CPU_1x clock rate
  • Master mode for DMA transfers (with 1 KB FIFO)
  • Slave mode for register accesses
SDIO Specification 2.0
  • Low-speed, 1 KHz to 400 KHz
  • Full-speed, 1 MHz to 50 MHz (25 MB/sec)
  • High-speed and high-capacity memory cards

ZynqMP/Versal

Compliance
  • SD Host Controller Standard Specification Version 3.00
  • SDIO card specification Version 3.0
  • SD Memory Card Specification Version 3.01
  • SD Memory Card Security Specification version 1.01
  • MMC Specification version 4.51
  • OCP specification version 2.01(For the Host Controller with OCP Interface)
  • AMBA AHB Specification version 2.00 (For the Host Controller with AHB Interface)
  • AMBA AXI Specification version 3.00 (For Host Controller with AXI Interface)
System/Host Interface
  • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
  • Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP Interface.
SD/SDIO Card interface
  • Host clock rate variable between 0 and 208 MHz
  • Up to 832Mbits per second data rate using 4 parallel data lines (SDR104 mode)
  • Transfers the data in 1 bit and 4 bit SD modes
  • Transfers the data in SDR104, SDR50, DDR50 modes.
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Variable-length data transfers
  • Performs Read wait Control, Suspend/Resume operation SDIO CARD.
  • Designed to work with I/O cards, Read-only cards and Read/Write cards
  • Supports Read wait Control, Suspend/Resume operation
MMC card interface
  • Host clock rate variable between 0 and 208 MHz
  • Up to 1664Mbits per second data rate using 8 bit parallel data lines (mmc8 bit SDR mode)
  • Up to 832Mbits per second data rate using 8 bit parallel data lines (mmc8 bit DDR mode)
  • Transfers the data in 1 bit, 4 bit and 8 bit modes
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Supports MMC Plus and MMC Mobile
  • Card Detection (Insertion / Removal)

What's new in Zynqmp/Versal
  1. SD
    • UHS speed modes
    • 1.8V capability
    • SDXC card capacity support (>64G)
    • Tuning procedure for SDR104/DDR50/SDR50
    • voltage switch, tuning commands
  2. eMMC
    • complete new spec handled by JEDEC compared to MMC association
    • HS200 mode and Extended CSD register to support various features
    • 1.8V/1.2V support from CMD0
    • DDR mode support
    • 8-bit bus width
    • Tuning, bus width testing procedures
    • variants of erase - secure/trim/discard/sanitize
    • boot partitions, boot mode alternate boot mode
    • RPMB partitions

Features supported by driver

Zynq

  • All the HW/IP features are supported by driver

ZynqMP


  • All the HW/IP features are supported by driver

Versal


  • All the HW/IP features are supported by driver

Missing features, known Issues, limitations

  • SD UHS modes support is disabled in the driver currently due to board and silicon dependencies. Not all boards are having 3.0 level shifter

Kernel configurations

Devicetree

SD and eMMC

Performance

SD card : Sandisk Ultra 16GB SDHC card

Zynq:
High speed20.54 MB/secread speed, tool: hdparm
ZynqMP:
High Speed19.4 MB/Secread speed, tool: hdparm
UHS (SDR)SDR104: 76.50MB/secread speed, tool: hdparm
UHS (DDR)DDR50: 40.68MB/secread speed, tool: hdparm
Note : ZynqMP platform will support 'High Speed' mode by default. To operate the SD on UHS (Ultra High Speed) modes, please click here.

Test Procedure

Read/Write test using File System
Read/Write test using DD commands
Create partition using FDISK
Testing the eMMC RPMB Partition

The eMMC RPMB partition can be tested by using mmc-utils tool.

Please note that writing the authentication key to the RPMB partition is one-time programmable (irreversible) change.


Expected output

Boot log for SD
Boot log for EMMC

Mainline Status

The SD driver is currently in sync with mainline kernel v5.10.
Fixes related to coverity warnings, reading taps from dts file, auto tuning for DDR50, manual tuning (~30 lines) 

Change Log

2016.3
Summary:
  • Added support for Tap delays required for 3.0 modes and high speed modes.
  • Added new workaround for auto tuning.
  • Added "SDHCI_QUIRK_BROKEN_ADMA" quirk to the sdhci arasan controller based on DT property. With 4.6 kernel ADMA2 is broken on Zynq, so added this quirk as a workaround and can be reverted once it is fixed.
Commits:
0fb3161d0a60 - mmc: sdhci-of-arasan: Add support for tapdelay programming
ba35b69e41d0 - mmc: sdhci-of-arasan: Added workaround for auto tuning
0e4e40714931 - mmc: arasan: Add ADMA broken quirk based on DT parameter

2016.4
Summary:
  • None

2017.1
Summary:
  • Add pinctrl support to the driver
Commits:
3feb3b18c249 - mmc: arasan: Add pinctrl support to the driver

2017.2
Summary:
  • None

2017.3
Summary:
  • Added support for switching to UHS-I modes on ZynqMP Platform
  • Reverted "mmc: arasan: Add ADMA broken quirk based on DT parameter"
Commits:
dcbfca5021bb - sdhci: add support for switching to UHS-I modes on ZynqMP Platform
f9658a41c361 - Revert "mmc: arasan: Add ADMA broken quirk based on DT parameter"

2017.4
Summary:
  • None

2018.1
Summary:
  • None

2018.2
Summary:
  • Removed quirk for broken base clock in SDHCI driver
  • Added runtime PM support in SDHCI driver
Commits:
f18d4e43c908 - Remove quirk for broken base clock
f7225b8f1108 - Add runtime PM support
2018.3
Summary:
  • Added support to read Tap Delay values from DT

Commits:
5a0f5d4c5b35 - Add support to read Tap Delay values from DT

2019.1
Summary:

  • None

2019.2
Summary:

  • Updated driver to make use SDHCI framework API for auto tuning

Commits:

c1e2062e131e- Updated driver to utilize the SDHCI framework API


2020.1
Summary:

  • Modified the SDHCI Arasan driver to be in sync with Linux v5.4 mainline kernel
  • Implemented the SD Tap Delays support in a generic way.
  • Added Versal Tap Delays support

Commits:

6caf07207d79 - mmc: sdhci-of-arasan: Add support to set clock phase delays for SD

28e8d44fc74d - sdhci: arasan: Add support for Versal Tap Delays


2020.2
Summary:

  • Modified the driver to fix timings allocation code
  • Modified the driver to comply with coverity
  • Fixed tap delay related minor issues

Commits:

523ef87e7a6f - mmc: host: sdhci-of-arasan: fix timings allocation code

65f2da370e37 - mmc: host: sdhci-of-arasan: Check return value of non-void funtions

d07083bd15e8 mmc: host: sdhci-of-arasan: Use appropriate type of division macro

a739e1ec7d3b mmc: host: sdhci-of-arasan: Resolve uninitialized return value

b7270346ab4b mmc: host: sdhci-of-arasan: Modify data type of the clk_phase array

8ed795ce9826 mmc: sdhci-of-arasan: Allow configuring zero Tap values

fee3d70413aa mmc: sdhci-of-arasan: Use Mask writes for Tap delays

c96093c17fd8 mmc: sdhci-of-arasan: Issue DLL reset explicitly


2021.1
Summary:

  • Fix the issue in reading the tap delay values from Devicetree.

Commits:

1007e369c036 - Fix the issue in reading tap values from DT

Related Links

Source file link:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/mmc/host/sdhci-of-arasan.c