ZynqMP OCM EDAC Driver

Owned by Confluence Wiki Admin (Unlicensed)
Last updated: Nov 13, 2024 by Datta, Shubhrajyoti
This page gives an overview of Zynqmp/ Versal OCM EDAC driver which is available in Xilinx Linux distribution as drivers/edac/zynqmp_ocm_edac.c

Overview

The on-chip memory (OCM) module contains 256 KB of RAM. It supports a 128-bit AXI slave interface port. The OCM has eight exclusive access monitors that
allow the OCM to simultaneously monitor up to eight exclusive access transactions. The OCM supports high AXI read and write throughput for RAM access by
implementing the RAM as a double-width memory (256 bits). The OCM implements double-width memory to maximize the read and write bandwidth. Maximum
bandwidth is achieved when the read/write accesses are a multiple of 256 bits with 256-bit aligned addresses. The Xilinx memory protection unit (XMPU) is
supported at 4KB memory granularity. The entire 256 KB of RAM can be divided into 64 blocks (4KB each), and assigned security attributes independently.
Arbitration between the read and write channels of the OCM switch ports is performed within the OCM module. OCM supports a 64-bit ECC.

HW/IP Features

  • supports a 64-bit ECC
  • Single bit error detection and correction
  • Double bit error detection
  • Error injection support

Driver Features

  • Detects and reports the errors on OCM
  • Supports error injection for both countable and uncountable errors

Missing features, Known Issues and Limitations

  • NA


Kernel Configuration

The following config options should be enabled in order to build ZynqMP OCM EDAC driver:
config EDAC_ZYNQMP
	tristate "Xilinx ZynqMP OCM Controller"
	depends on ARCH_ZYNQMP || COMPILE_TEST
	help
		This driver supports error detection and correction for the
		Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
		built as a module. In that case it will be called zynqmp_edac.

Devicetree Settings

Example:
ocm: memory-controller@ff960000 {
           compatible = "xlnx,zynqmp-ocmc-1.0";
           reg = <0x0 0xff960000 0x1000>;
           interrupt-parent = <&gic>;
           interrupts = <0 10 4>;
};

Mainline Status

mainlined

Testing Procedure

The general guideline is that the user chooses an address for testing that is not used by the system.

For versal:

Unlike ZynqMP, BOOT ROM is not doing the below required configuration/initialization for OCM in Versal platform.

-> Enable ECC for OCM

-> Initialization of OCM

If OCM ECC is not enabled in the design, use the below CDO  which enables the ECC for OCM and initialize the OCM memory.

ecc.cdo

Add this CDO to the lpd section in the bif file along with lpd_data.cdo as shown below and create PDI.

name = lpd
  id = 0x4210002
  partition
  {
   id = 0x0C
   type = cdo
   file = gen_files/lpd_data.cdo
   file = <path>/ecc.cdo
  }


After linux boot, just give the below command to make sure for driver probing
root@Xilinx-ZCU102-2017_3:~# dmesg | grep EDAC
[    2.012025] EDAC MC: Ver: 3.0.0
[    2.015146] EDAC DEBUG: edac_mc_sysfs_init: device mc created
[    3.818896] EDAC DEBUG: edac_device_register_sysfs_main_kobj:
[    3.818915] EDAC DEBUG: edac_device_add_device:
[    3.818919] EDAC DEBUG: find_edac_device_by_dev:
[    3.818923] EDAC DEBUG: edac_device_create_sysfs: idx=0
[    3.818936] EDAC DEBUG: edac_device_create_instances:
[    3.818956] EDAC DEVICE0: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
This driver creates edac device controller in sysfs /sys/devices/system/edac/ directory as zynqmp_ocm

To inject CE Errors

Configure the bit position to generate CE Error

# echo 4 > /sys/kernel/debug/edac/ocm/inject_fault_count
# echo 31 > /sys/kernel/debug/edac/ocm/inject_ce_bitpos
Write any data to any OCM Memory area, so at the time of writing data the controller injects errors and will report when you read back
the location
# devmem 0xfffd0000 64 0xFFFFFFFFFFFF
 
read back the data
# devmem 0xfffd0000
[  379.903651] EDAC DEVICE0: CE: zynqmp_ocm instance: zynqmp_ocm0 block: zynqmp_ocm0 '
OCM ECC error type :CE
Addr: [0xFFFD0000]
Fault Data[31:0]: [0x7FFFFFFF]
Fault Data[63:32]: [0xFFFF]'
0x0000FFFFFFFFFFFF
here we have written 0xFFFFFFFFFFFF and configured bitposition as 31 for CE, so bit 31 it will inject
CE and corrects that bit
Actual Data Written: 0xFFFFFFFFFFFF
Fault Data         : 0xFFFF7FFFFFFF

To inject UE Errors

Configure the bit positions to generate UE Error
 
# echo 4 > /sys/kernel/debug/edac/ocm/inject_fault_count
# echo "7,32" > /sys/kernel/debug/edac/ocm/inject_ue_bitpos
Write any data to any OCM Memory area, so at the time of writing data the controller injects errors and will report when you read back
the location
# devmem 0xfffc0000 64 0xFFFFFFFFFFFF
# devmem 0xfffc0000
[   64.973665] Unhandled fault: synchronous external abort (0x92999219) at 0x0000007f9182b000)
[   64.973674] EDAC DEVICE0: UE: zynqmp_ocm instance: zynqmp_ocm0 block: zynqmp_ocm0 '
OCM ECC error type :UE
Addr: [0xFFFC0000]
Fault Data[31:0]: [0xFFFFFF7F]
Fault Data[63:32]: [0xFFFE]'
0x0000FFFEFFFFFF7F
here we have written 0xFFFFFFFFFFFF and configured bitposition0 as 7 and bitposition1 as 32,
so a  ctual Data Written: 0xFFFFFFFFFFFF
Fault Data              : 0xFFFEFFFFFF7F

Expected Output


root@Xilinx-ZCU102-2017_3:~# echo 1 > /sys/kernel/debug/edac/ocm/inject_cebitpos
root@Xilinx-ZCU102-2017_3:~# echo 4 > /sys/kernel/debug/edac/ocm/inject_fault_count
root@Xilinx-ZCU102-2017_3:~# devmem 0xfffc0000 32 0x1234
root@Xilinx-ZCU102-2017_3:~# devmem 0xfffc0000
[   63.623644] EDAC DEVICE0: CE: xlnx,zynqmp_ocmc-1.0 instance: zynqmp_ocm0 block: zynqmp_ocm0 '
OCM ECC error type :CE Addr: [0xFFFC0000] Fault Data: [0x1236]'
0x00001234
root@Xilinx-ZCU102-2017_3:~# devmem 0xfffc0000
[   66.013637] EDAC DEVICE0: CE: xlnx,zynqmp_ocmc-1.0 instance: zynqmp_ocm0 block: zynqmp_ocm0 '
OCM ECC error type :CE Addr: [0xFFFC0000] Fault Data: [0x1236]'
0x00001234
root@Xilinx-ZCU102-2017_3:~#
root@Xilinx-ZCU102-2017_3:~#
root@Xilinx-ZCU102-2017_3:~# echo 4 > /sys/kernel/debug/edac/ocm/inject_fault_count
root@Xilinx-ZCU102-2017_3:~# echo "7,32" > /sys/kernel/debug/edac/ocm/inject_ue_bitpos
[ 1363.242555] EDAC ZynqMP-OCM: Set another bit position for UE, if not set
root@Xilinx-ZCU102-2017_3:~# echo 7 > /sys/devices/system/edac/zynqmp_ocm/inject_uebitpos1
[ 1377.012548] EDAC ZynqMP-OCM: UE at Bit Position0: 0 Bit Position1: 7
root@Xilinx-ZCU102-2017_3:~# devmem 0xfffe4200 32 0xFFFF
root@Xilinx-ZCU102-2017_3:~# devmem 0xfffe4200
[ 1406.443689] EDAC DEVICE0: UE: xlnx,zynqmp_ocmc-1.0 instance: zynqmp_ocm0 block: zynqmp_ocm0 '
OCM ECC error type :UE Addr: [0xFFFE4200] Fault Data: [0xFF7E]'
0x0000FF7E
root@Xilinx-ZCU102-2017_3:~#cat /sys/devices/system/edac/zynqmp_ocm/inject_uebitpos0
Fault Injection Data Reg: [0x81]
root@Xilinx-ZCU102-2017_3:~#
root@Xilinx-ZCU102-2017_3:~#
root@Xilinx-ZCU102-2017_3:~#cat /sys/devices/system/edac/zynqmp_ocm/zynqmp_ocm0/ue_count
2
root@Xilinx-ZCU102-2017_3:~#cat /sys/devices/system/edac/zynqmp_ocm/zynqmp_ocm0/ce_couny
1
root@Xilinx-ZCU102-2017_3:~#

Changelog

2024.2

  • None

2024.1

  • Summary
    • EDAC/zynqmp: Add EDAC support for Xilinx ZynqMP OCM
  • Commits

2023.2

  • None

2023.1

  • None

2022.2

  • None

2022.1

  • Summary
    • edac: zynqmp: Fix kernel doc format
    • edac: zynqmp: Use SPDX license header
  • Commits

2021.2

  • None

2021.1

  • None

2020.2

  • Summary
    • Minor update - Fix incompatible parameter error
  • Commits

2020.1

  • None

2019.2

  • None

2019.1

  • None

2018.3

  • None

2018.2

  • None


2018.1

  • None

2017.4

  • None

2017.3


2017.2

  • NA

2017.1

  • Summary
    • Fix hardcoding edac device index
  • Commits

2016.4

  • None

2016.3

  • None

Related Links

© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy