This page provides details related to the standalone tftps driver. This driver supports clockps Zynq Ultrascale+ MPSoC , microblaze and Zynq. For more information, please refer to  TRM (PG095) .

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2021.1 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/tft at xilinx_v2021.1 · Xilinx/embeddedsw

The driver source code is organized into different folders.  The table below shows the clockps driver source organization. 

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to (PG095) .

Features

Controller/Driver features supported

• The AXI TFT Controller is configured to the Chrontel CH-7301 chip only.

Known Issues and Limitations

NA

Example Applications

tft driver example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
embeddedsw/XilinxProcessorIPLib/drivers/tft at master · Xilinx/embeddedsw

Example Application Usage

Tft example

Tft example writes a character and draws a line.

Expected Output

Example Design Architecture

NA

Performance

NA

Change Log

2024.2

None

2024.1

None

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries