This page gives an overview of the bare-metal driver support for the Axi EMC driver.

Table of Contents

Introduction

The AXI External Memory Controller (EMC) IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to support the AXI4 interface.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/emc

The driver source code is organized into different folders.  The table below shows the emc driver source organization.

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer Axi EMC Controller data sheet: https://docs.amd.com/v/u/en-US/ds762_axi_emc

Features

The AXI EMC is a soft IP core designed for Xilinx FPGAs and provides the following features:

• Supports the AXI4 specification for AXI interfaces

• AXI4 slave interface supports 32-bit address bus and 32/64-bit data bus

• 32-bit configurable AXI4-Lite control interface to access internal registers

• Burst transfers of 1-256 beats for INCR burst type and 2, 4, 8, 16 beats for WRAP burst type

• AXI4 narrow transfers, unaligned transfer type of transactions

• Multiple (up to four) external memory banks

• Independent memory configuration of each memory bank

• Memory data widths of 64-bit, 32-bit, 16-bit and 8-bit for each of the memory banks

• Synchronous/Asynchronous SRAMs, Linear Page and Burst Mode NOR Flash, and PSRAM/Cellular RAM memory devices

• Configurable byte parity check for each of the memory banks for Synchronous / Asynchronous SRAMs

• Memory configuration, timing parameters, data width for each memory bank independently

• Configurable registers for PSRAM and Linear Flash in burst mode

Supported Flash vendors

• Intel

• Infineon

Change Log

2024.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.1/doc/ChangeLog#L883

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L27

2023.1

None

2022.2

None

2022.1

None

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries