Zynq-7000 AP SoC Spectrum Analyzer part 6 - AMS - XADC Signal Acquisition and DMA to L2 Cache & Complete Design Tech Tip 2014.3

Table of Contents

Document History

Description/Summary

Implementation

Block Diagram

Step by Step Instructions

Building the Hardware

Building the Software

Building the BOOT.BIN file:

Building the Application:

Testing the XADC hardware system

Conclusions

Document History

Description/Summary

In Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3" the FFT application developed in "Zynq-7000 AP SoC Spectrum Analyzer part 4 - Building and Running an FFT Tech Tip 2014.3" was enhanced by the addition of a hardware FFT implemented in the PL fabric of the Zynq-7000 AP SoC. This enabled us to compare execution times for the ARM processor, NEON SIMD engine and a pure hardware block, all computing the same FFT. The FFT application operates from data in an input table. Previously that data table was loaded with software generated data. In this Tech Tip, hardware will be added to the application in the PL to capture data from the on-chip Analog to Digital converter, the XADC block, connected to an AMS 101 or other appropriate analog input board.



This Tech Tip will illustrate the use of multiple DMA blocks and how the AXI interconnect can be used to funnel multiple processes into the ACP port of the PS. DMA operations are used for both moving the converted analog data into the PS and for filling and draining the hardware FFT block when that block is in use. This complication of the information flow is readily handled by the interconnect blocks in the PL design in coordination with the ACP port on the PS. Interrupts are used for signaling between the hardware blocks and the PS to reduce software overhead and demonstrate the ease with which interrupts can be used in a user application. In addition, this Tech Tip will demonstrate use of the IP Integrator (IPI) capability in Vivado 2014.3 for creation of the overall hardware system being utilized and coupling that to SDK for the software development and debug.

Implementation

Block Diagram

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This Tech Tip relies on information used in the AMS Targeted Reference Design and builds upon some of the software supplied with that design. An implementation block diagram within Vivado will show the overall structure in a later section of this Tech Tip. The XADC block is initialized for the selected sample rate and the channel corresponding to the AMS 101 card installed on the ZC702. A DMA engine and AXI Stream to Memory map block is interfaced to the XADC to move the sample data. An AXI Interconnect block provides the interface to the ACP port on the PS, providing arbitration and multiplexing between the XADC data and the data flowing to and from the hardware FFT block. Inside the PS, data from the XADC transfer is stored in the FFT input buffer until a buffer full has been accumulated. At that point, the FFT is invoked, either in software or the hardware FFT block, to process the sampled data.

Step by Step Instructions

This Tech Tip proceeds in two major operations; building the Hardware FFT and then building the software that controls and uses the Hardware FFT in conjunction with the software in the PS. Vivado is used to build the hardware in the PL while PetaLinux SDK and Vivado SDK are used to build the software application that manages the hardware blocks and software computation of the FFT when requested.

Building the Hardware

Vivado 2014.3 will be used to create the hardware FFT and XADC interface used in this Tech Tip. The hardware design elements for this Tech Tip are derived from the sources supplied with the ZC702 base Targeted Reference Design (TRD) for Vivado 2014.2. This enables us to use the IP Integrator capability in Vivado 2014.3 to build the hardware required for the FFT block and the XADC control and data movement hardware. Additional IP blocks are supplied to supplement the base TRD with functions required for the XADC capability. This set of sources is combined in the XADC2014dt3.zip file associated with this Tech Tip.

If you have not yet downloaded XADC2014dt3.zip, do so now. It is best to save this at the root of a hard drive to avoid problems with long path names. In our instance we downloaded and unzipped XADC.zip to G:\XADC - the default if XADC.zip is saved to the root of the drive.

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The base directory where the HWfft.zip files are saved is referred to as $ZYNQ_XADC_HOME. In our case then $ZYNQ_XADC_HOME is G:\XADC. If you have a different base directory, note that it will be used where $ZYNQ_XADC_HOME is referenced.

Supplied with this Tech Tip is a tcl script file that will simplify the process of building the FFT and XADC support hardware in Vivado. This file is:

project.tcl

The script file is in the /scripts sub directory where XADC was unzipped. In our case this is G:\XADC\scripts or

$ZYNQ_XADC_HOME/scripts

We now run Vivado to build the hardware system.

On Windows, select Start > All Programs > Xilinx Design Tools > Vivado 2014.3 > Vivado 2014.3

Vivado will start and show the welcome screen

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CAUTION:
Before starting the process of building the hardware, verify that you have installed valid hardware licenses for the IP cores used in the ZC702 Base TRD design. These include the Chroma-Resampler, Video Timing Controller, etc. (See the Base TRD user guide for more information.) If a hardware implementation license is not in place when bitstream generation starts, the whole project will need to be deleted and started from the beginning.

In the tcl console input line, run the following commands

cd $ZYNQ_XADC_HOME

source . /scripts/project.tcl

The project.tcl should build the complete base TRD hardware system with the PS and various video processing hardware blocks used by the TRD software. In addition, it will add the FFT hardware block from the Tech TIp "Zynq Adding Hardware FFT Tech TIp" and the XADC block with additional hardware DMA support.

If you encounter any licensing issues or other implementation errors in running the project.tcl script, these must be resolved before running continuing. Otherwise the hardware will not build properly.

With this tcl script complete, the hardware FFT and XADC have been added to the system and connected to the PS as shown below

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IP Integrator has both placed the functional blocks but also connected them with their corresponding signal bundles to the other blocks in the design. This greatly simplifies the process of generating a complex design and assuring that the components are connected properly. Any block of logic created from scratch or configured within Vivado can be saved as a reusable IP core for later use. See the Vivado IP Integrator documentation for details on how this is done.

In the block diagram pane, we can zoom into the XADC hardware to see what it contains. Move the cursor to hover over the upper left corner of the XADC block. When it changes to double chevrons, click to expand the hierarchy of the XADC IP core.

Using the zoom controls, either the magnifying glass with the + or selecting and dragging a zoom window in the diagram pane, zoom in to better see the contents of the XADC block. You can also maximize the diagram pane (click the maximize icon in the upper right corner) if desired.

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The XADC block is a standard IP core that is configured through the Core Generator. In this instance it is configured to be controlled from the SPI interface that is exposed in the PS. This will enable us to use software to select the various possible inputs, set the sample rate, etc. When the software is built later in this Tech Tip, setup code from a reference design for the XADC block will be reused. This is facilitated by the use of the same physical and logical connections from the PS to the XADC core.

The axi_dma block previously seen in the hardware FFT implementation is used to move the data from the XADC into the FFT core. The AXI interconnect block is also used to move the data to the ACP port of the PS. The AXI interconnect handles any multiplexing and arbitration between the two AXI streams of data; from XADC and from the FFT processing block. In addition it handles the translation from streaming data, used by the FFT block to memory mapped data required to interface to memory in the PS through the ACP port.

The xlconcat block is used to vectorize the various interrupt sources in the design. For proper operation, interrupts from the PL to the PS must be enabled. To verify this, we examine the configuration of the ZYNQ7 Processing System block.

Double click on the Zynq block to enter it's configuration screens.

From the items in the left column, select "Interrupts" and click on it.

Expand the Fabric Interrupts item and the PL-PS Interrupt Ports line

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Note the range of interrupt numbers that are assigned to the IRQ-F2P inputs. As can be clearly seen, they are assigned to the higher order bits first; the first is 91, then 90, etc. These are the ARM A9 hardware interrupt numbers and are numbered differently in Linux. This will be noted later in discussing the device tree used by the kernal to manage the interrupts.

Also, the interrupt numbers are not contiguous, but that is not of concern for this application.

By expanding the PS-PL Interrupt Ports line, you can see that none of the possible interrupts from the PS into the Fabric are enabled; they are not used in this application.

With the interrupts enabled, we need to verify that they are connected properly in the hardware.

While the interrupts in the hardware are scaler items, the Interrupt handler in the PS expects a vector of interrupts. The Concat block will be used to concatenate all of the interrupt sources into a vector to be supplied to the IRQ_F2P port.

Exit from the Zynq Processing System configuration screen by hitting the Cancel button.

Double click on the Concat block (xlconcat_1) to enter its configuration screen.

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In addition to interrupts already used in the TRD, we have added signals to monitor the read and write channels of the DMA used in the FFT block and the XADC block.

No changes to the Concat block are needed at this time so it can be exited by clicking the Cancel button.

While the build script has connected the interrupt sources to the Concat block, they may not be shown in the Block Design view within Vivado.

If the Block Design is not shown, click Open Block Design under IP Integrator in the Flow Navigator at the left side of the Vivado window.

With the Block Diagram shown, click on the icon at the top left corner of the Block Design Window adjacent to Block Design Options.

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The items to be displayed will be listed. If display of interrupts is currently enabled (a check mark next to them) and they are not shown, simply disable and re-enable them.

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We can now see the various interrupt sources connected to the Concat block

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We will also need to know the location of the control registers used to manage the DMA block associated with the XADC. These are set properly by the build script so this step is just to illustrate how to check the addresses.

Click on the Address Editor tab at the top of the block design display window.

The address map of the hardware in the system will be shown. Note the address range for the AXI LITE interface for the XADC_1/axi_dma_1.

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Return to the block design diagram by clicking on the Diagram tab on the block design display window.

To complete the hardware design, synthesis and implementation must be run. This can be done by initiating each step individually or if "Generate Bitstream" is selected, the Synthesis and Implementation steps will be run automatically.

In the flow Navigator panel, click Generate Bitstream (in the Program and Debug group at the bottom of the panel)

Synthesis, implementation and bitstream generation may take as long as two hours for this design. There will be some warnings, but these are not critical to the proper operation of the hardware. If there are any Launch Critical Warnings, simply click OK to accept them and allow Synthesis to continue.

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When Vivado completes processing the design, verify that there are no errors; warnings are expected with most relating to optimizations that are being done and have no impact on operation of the hardware. In the "Bitstream Generation Completed" accept the "Open Implemented Design option and click OK.

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Vivado will then display the chip view of the implemented design

The next step is to export this hardware design in a form that SDK can use to build the files needed to properly configure the ZC702 to run the hardware FFT.

From the File menu select

File > Export > Export Hardware...

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In the dialogue box that appears, leave the defaults selected and click OK. The option to Include bitstream should be visible and checked. This is convenient as it enables Vivado to put all of the information required in a single file.

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Vivado creates a hardware description file in a directory branch off of the "project" area as shown below. The file in this branch will be used in the next step so remember where it is. (You may be prompted to save the project before the hardware is exported.)

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At this point, we are done with Vivado and it can be closed. Save the project for future reference if prompted.

Building the Software

With the hardware for the FFT and the XADC block in the PL fabric complete and included in the base TRD hardware, we need to build the software to control the XADC and move data through the interconnect to the ACP port. Data received at the ACP port from the XADC operation will be placed in the FFT input table in the PS memory. When data receipt is complete, the DMA signals the PS of this action. In addition we will include the software developed in an earlier Tech Tip in this series to move data into and out of the FFT block. Recall from the block diagram that the data movement in the PL is controlled by DMA blocks. The software for operating the hardware FFT is simply the driver to start the DMA and to service the interrupts that are generated by the DMA block when it is complete. For the XADC block, software is used to set up the XADC through the control interface and to set up the DMA that moves the data into the ACP port. For the purposes of this Tech Tip, simple polling is used to monitor progress of the DMA associated with the XADC operation.

Building the software will be done in two separate steps; building a new boot file that includes the hardware for the XADC block and then separately building the application that controls the overall XADC operation and display of the results.

Building the BOOT.BIN file:

For this Tech Tip, interrupts are not being used for the interface to the XADC block. Therefore, the only boot file that needs to be built is the BOOT.BIN as it contains the bitstream which has the new hardware in the PL. In the previous Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 6 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3" the PetaLinux SDK was used to build both the BOOT.BIN and image.ub files. For this Tech Tip, we can use Vivado SDK because we are not building the image.ub file. Since we are only changing the bitstream portion of the BOOT.BIN, we will use a first stage boot loader (fsbl) and u-boot.elf files used by the PetaLinux system for the same operation.

The base TRD for the ZC702 that utilizes PetaLinux is described in the technical article Zynq Base TRD 2014.2 Follow the instructions found there to download the software from the Xilinx web site. Unzip the set of files to a convenient place on your computer. In our case, we put them in our "Projects" folder:

G:\Projects\rdf0286-zc702-zvik-base-trd-2014-2

If we look inside this folder, we can see a variety of files but a fsbl and u-boot.elf are not readily apparent. However, there is a large file with the extension of .bsp that is in the petalinux folder. Normally this is used to set up a project within the PetaLinux development environment. For our use, we are going to extract the needed boot files from this .bsp file.

G:\Projects\rdf0286-zc702-zvik-base-trd-2014-2\software\petalinux\bsp\Xilinx-zc702-trd-v2014_2.bsp

While we could extract the contents at the current location, to be sure we do not disturb the integrity of the TRD, we simply copy the .bsp file to another location. Once that is done, change the extension to .tar (this file is really a compressed Linux compatible file). Then we can use a standard tool to "un-compress" the file, resulting in the following set of folders withing the extracted archive.

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If we then drill into the pre-built folder to linux and then images, we can find the following set of files

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From within SDK, we will simply use the now readily visible zynq_fsbl.elf and u-boot.elf files along with the new bitstream to build the required new BOOT.BIN file.

At the conclusion of the Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3" the workspace contains the library of signal processing functions built in the Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 2 - Accelerating Software - Building ARM NEON Library Tech Tip 2014.3"and tested in the Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 2 - Accelerating Software - Running ARM Library Tests Tech Tip 2014.3". It also has the tested application code for the FFT application including the hardware FFT. This Tech Tip is built upon that existing workspace. If you have that workspace in place,skip forward in these instruction to where the workspace is in place (Old Workspace in Place).

If the workspace is not available, or if there is an question if it was completed properly (or you simply want to skip those earlier steps), the referenced file HWfft_workspace2014dt3.zip can be used to create a known working starting point for the software portion of this Tech Tip.

Download the zip file from the HWfft_workspace2014dt3.zip link.

Create an empty directory where you will be implementing this Tech Tip. To be consistent with the balance of these step by step instructions, the directory could be:

G:\Projects\ZC702_Ne10

However, these steps to import a known workspace will work with any new folder of the user's choosing.

CAUTION:
Many users have unusual problems with SDK when using different directory structures or names. If you encounter any odd behaviors with SDK, it is advised to use the suggested directory structure and names.

Start SDK

Start -> All Programs -> Xilinx Design Tools -> Vivado 2014.3 -> Xilinx SDK 2014.3

In the Workspace Launcher, browse to and select the previously created empty folder. In our case, that is G:\Projects\ZC702_Ne10

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Click OK to continue

If you are presented with a Welcome tab, close it by clicking on the x on the tab.

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SDK will start with a blank Project Explorer pane

Select File -> Import

The Import dialogue box will appear. Expand the General line and select Existing Projects into Workspace

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Click Next

Click the Select archive file button. Then click Browse to navigate to the saved workspace file that you want to import and click Open. In our case this is HWfft_workspace2014dt3.zip.

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Click Finish

SDK will build the workspace automatically. If it does not, simply select Project -> Build All

Because SDK is now running and the workspace is in place, you can skip the following instructions on starting SDK and go directly to after SDK is running and the workspace is in place (Starting Projects Ready).

Old Workspace in Place

The first step in building our new BOOT.bin is to bring the new hardware information from Vivado into SDK. We start with the workspace that resulted from the completion of the "Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3".

Start SDK

On Windows, select Start -> All Programs -> Xilinx Design Tools -> Vivado 2014.3 -> Xilinx SDK 2014.3

When the Workspace Launcher appears, be sure that it is pointed to the workspace used for the "Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3".

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Click OK

Starting Projects Ready

SDK should have the files and projects in place as we last saw them. If it has changed, use the known workspace from the steps above or repeat the various steps to be sure this is a tested working set of files and projects before proceeding.

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The new hardware from Vivado will impact the standalone_bsp and the hardware platform (ZC702fft in our case) which in turn are key in building any hardware dependent applications, such as the XADC test software. These changes also would impact creating of new files for building a new BOOT.bin but we will not need to do that here as we will extract them from the PetaLinux build package as described earlier.

Select the hardware platform - in this case we have called it ZC702ff - in the Project Explorer pane, right click on it and select "Change Hardware Platform Specification". When the pop up box appears, read the cautions and click Yes.

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Click Browse and follow the path from the $ZYNC_XADC_HOME used earlier to \project\zynq_base_trd_2014.3.sdk

SDK will show system_top_wrapper.hdf as an available file.

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Select system_top_wrapper.hdf

Click Open and then OK in the "Change Hardware Platform Specification" dialog

SDK will process the new Hardware Description File (.hdf) and update the current platform.

To verify this update, expand the ZC702fft line in the Project Explorer pane and double click on system.hdf. SDK will display the current information about the hardware system. Note the presence of several items relating to XADC, and note the address of the XADC_1_axi_dma_1 which we noted earlier in examining the hardware from within Vivado.

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To complete the inclusion of the new hardware information we need to re-build the Board Support Package (bsp). In this case this is the project called standalone_bsp_0 (Note that it has a different leading icon to indicate it is a board support package.).

There are two approaches to updating the Board Support Package. One way is to delete the current bsp from the system (if you do this be sure to check the selection box to delete it from your computer), and build it from scratch as was shown in an earlier Tech Tip. The second approach used here is to force a regeneration from the hardware platform.

Select standalong_bsp_0 in the Project Explorer pane. Right click and select Re-generate BSP Sources. This will update the BSP with appropriate interfaces and drivers for the new hardware.

When that is finished, right click on standalong_bsp_0 again and select Clean Project. When that is finished, right click on it again and select Build Project.

The build process will create an error similar to the following:

xsysmon_g.c:53:3: error: 'XPAR_XADC_1_XADC_AXIS_FIFO_ADAPTER_1_IP_TYPE' undeclared here (not in a function) XPAR_XADC_1_XADC_AXIS_FIFO_ADAPTER_1_IP_TYPE At this time, the cause of this error is under investigation. However, it can be readily remedied. In the Project Explorer pane, navigate into the standalone_bsp_0 project to the following: standalone_bsp_0 -> ps7_cortexa9_0 -> libsrc -> sysmon_v7_0 -> src -> xsysmon_g.c Double click on xsysmon_g.c to open it in an edit window in SDK