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ZDMA

ZDMA

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Last updated: Jun 11, 2025 by Joseph, Abin



ZDMA Linux Driver

Introduction

This page gives an overview of Zynqmp and Versal DMA which is available in Xilinx Linux distribution and in open source linux as drivers/dma/xilinx/zynqmp_dma.c
Xilinx General Purpose DMA is designed to support memory to memory and memory to devices and device to memory transfers.
ZynqMP Ultrascale has two instance of DMA . One located in FPD (full power domain) is GDMA and the other located in LPD (low power domain) is ADMA.

Total 16 DMA channels (8 GDMA + 8 ADMA) are available.

Versal and Versal Gen 2 have one instance of this DMA located in LPD (low power domain) called ADMA with 8 channels.

HW IP features

  • AXI 4 support , burst length is limited to 16 to provide AXI 3 compatibility

  • SRC and DST payload can start and end at any alignment

  • Over fetching can be enabled/disabled per channel

  • Up to 8 configurable DMA channels

  • Each channel can be programmed secure or non-secure

  • Programmable number of outstanding transactions per channel

  • Support for periodic transaction scheduling. Period can be independently programmed per channel

  • Supports Simple(descriptor less) and Scatter Gather (SG) DMA modes

  • Supports read only DMA mode

  • Supports write only DMA mode

  • Common Buffer is automatically shared among all enabled DMA channels

  • Support for DMA START, STOP and PAUSE

  • Interrupt Accounting support

  • Descriptor prefetch support to maximize DMA efficiency

  • Support for error recovery

  • INCR & FIXED type burst supported

  • Independent AXI burst length is supported on SRC & DST Side

  • Support for per channel flow control interface

Features supported in driver

  • Memory to Memroy transfers are support

  • Scatter Gather (SG) DMA mode is supported with assumption of contiguous memory; this is because DMA_SG support in linux framework was removed in mainline kernel as there are no consumers.

  • Optional descriptor's coherence.

  • Optional AXI burst length is supported for both DST and SRC side. Supported values are only power of 2 i.e 1,2,4,8 and 16

  • Support 8 DMA Channels

  • Interrupt Accounting Support.

Missing Features and known Issues/Limitations in Driver

  • No support for flow control mode.

  • No support for linear and hybrid descriptor modes

  • No Support for Simple DMA mode

Kernel Configuration

The following config options should be enabled in order to build ZynqMP/Versal DMA driver:

config XILINX_ZYNQMP_DMA tristate "Xilinx ZynqMP DMA Engine" select DMA_ENGINE help Enable support for Xilinx ZynqMP DMA controller.

The following config options should be enabled inorder to build dmatest client

config DMATEST tristate "DMA Test client" help Simple DMA test client. Say N unless you're debugging a DMA Device driver.

For testing with multiple scatter gather sources following option should be enabled.

config DMA_ENGINE_RAID

Devicetree

Each channel is treated as independent device so for every channel there should be separate devicetree entry.

For more details please refer to devicetree documentation here: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/dma/xilinx/xlnx%2Czynqmp-dma-1.0.yaml
Example:

fpd_dma_chan1: dma@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <0>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; lpd_dma_chan1: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <0>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; };

NOTE: Please note the change in ZDMA compatible string for Versal Gen 2 devices as there are minor interrupt register related differences

amd,versal2-dma-1.0 is used for Gen 2 devices while xlnx,zynqmp-dma-1.0 is used for all previous families. This distinction is required because Versal Gen 2 device has different register offsets for interrupt Enable, Disable, Mask, and Status operations, which are not compatible with the register offsets and fields used in previous devices.

Test Procedure

There is a generic dma test client driver availble here @ https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/dmatest.c
For more details about how to use this test client find details here @ https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/driver-api/dmaengine/dmatest.rst

Mainline status

The current driver available in the AMD(xilinx) distribution is in sync with the open source except for the following:

  • Reset configuration handling for ADMA channels. This will be replaced with an upstreamable solution in a future release



Change Log

2025.1

Summary

  • 6.12 rebase and fix for reset configuration registers for ADMA channels

Commits

History for drivers/dma/xilinx/zynqmp_dma.c - Xilinx/linux-xlnx

2024.2

Summary

  • Add support for Versal Gen 2 DMA

Commits

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2024.2/drivers/dma/xilinx/zynqmp_dma.c

2024.1

No Changes

2023.2

None

2023.1

  • Add device_synchronize support to allow proper termination of transfers

  • Mainline updates including descriptor callback changes

  • Minor coverity fixes

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2023.1/drivers/dma/xilinx/zynqmp_dma.c

2022.2

No changes

2022.1

No changes; rebased on 5.15 kernel

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2022.1/drivers/dma/xilinx/zynqmp_dma.c

2021.2

No changes

2021.1

Summary

  • Minor warning fixes.

Commits:

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2021.1/drivers/dma/xilinx/zynqmp_dma.c

2020.2

No changes

2020.1

Summary

Minor bugfixes including:

  • Fix descriptor list handling during reset.

  • Phase dma_zalloc_coherent.

Commits:

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2020.1/drivers/dma/xilinx/zynqmp_dma.c



2019.2

None



2019.1

None

(Upgraded to mainline 4.19)



2018.3

None

2018.2

None

2018.1
Summary:

  • Fixed race condition in the probe, in case of interrupt property is not present, driver is trying to free an invalid free.

Commits:
968167b: dma: xilinx : Fix race condition in the probe

2017.4

None

2017.3
Summary:

  • Fixed issue driver does not work when CONFIG_PM is not set and ignore_unused is not passed.

  • Fixed race conditions in the prep_sg

Commits:
6589fe8 : dma: xilinx: zynqmp_dma: Enable clocks even when CONFIG_PM is disabled
bbd4291 : zynqmp_dma: Fix race condition in the prep_sg

2017.2

None

2017.1
Summary:

  • Fixed issues with overflow interrupt

  • Added runtime PM support in the driver

  • Fixed kernel doc warnings in the driver

  • Fixed sparce warnings in the driver

Commits:
55d3651 dma: zynqmp_dma: Fix issues with overflow interrupt
4b81f5a dma: zynqmp_dma: Add runtime pm support in the driver
0a4fb79 dma: zynqmp_dma: Fix kernel-doc format
a3848d4 dma: zynqmp_dma: Fix warning variable val set but not used

2016.4
Summary:

  • Added missing clock nodes for LPDDMA in zynqmp-clk.dtsi and zynqmp.dtsi files

  • Updated the description for LPDDMA Channel usage in the zynqmp.dtsi

Commits:
97f4d4e : Add missing clock nodes for lpddma in zynqmp-clk.dtsi and zynqmp.dtsi files
4996e76 : Add description for LPDDMA Channel usage

2016.3
Summary:

  • Driver got mainlined in the 4.8 kernel version

  • Existing driver in the xilinx linux distribution is in sync with the mainline driver

  • Added support for Scatter/Gather feature support in the generic DMA test client driver

  • Deleted the zynqmp_dmatest client driver as it is similar to the generic test client driver after adding support for the SG.

Commits:
cd23261: commit: Sync driver with mainline
8685d21 : commit: Fix Static Checker warning
1f31af6 : commit: Remove zynqmp_dmatest driver

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