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Common Clock Framework for Zynq Ultrascale+ MPSOC

Common Clock Framework for Zynq Ultrascale+ MPSOC

This page gives an overview of the Zynq Ultrascale+ MPSoC Clock framework available at drivers/clk/zynqmp/. For CCF to work, PMUFW should be downloaded.



Table of Contents



HW IP features



The Zynq® UltraScale+™ MPSoC has a programmable clock generator that takes a clock of a definite input frequency and generates multiple derived clocks using the phase-locked loop (PLL) blocks in the processing system (PS). The output clock from each of the PLLs is used as a reference clock to the different PS peripherals. Clocking Features The Zynq UltraScale+ MPSoC has five PLLs that generate various clocks used in the PS subsystem:

  • DDR PLL (DPLL): mainly used to generate clocks for the DDR controller.

  • APU PLL (APLL): mainly used to generate clocks for the APU.

  • RPU PLL (RPLL): mainly used to generate clocks for the RPU.

  • I/O PLL (IOPLL): mainly used to generate clocks the peripheral I/Os.

  • Video PLL (VPLL): generates clocks for the video blocks used in the PS subsystem.

These PLLs can be used to generate the output clocks.  It is recommended that we reserve VPLL for dp_video_ref.

Features Supported in the Driver



  • Clock gating

  • Clock scaling

Missing features, Known Issues, limitations

  • We do not support shared peripherals. (e.g. when the same peripheral is shared between A53 and R5 etc.)

Important AR links

  • Recommend to reserve VPLL for dp_video_ref if DP video is used AR - AR-69345

Kernel Configuration

The following config options should be enabled in order to build the ccf driver

CONFIG_COMMON_CLK_ZYNQMP

Symbol: COMMON_CLK_ZYNQMP [=y] │ │ Type : boolean │ │ Prompt: Support for Xilinx ZynqMP Ultrascale+ clock controllers │ │ Location: │ │ -> Device Drivers │ │ (1) -> Common Clock Framework │ │ Defined at drivers/clk/zynqmp/Kconfig:1 │ │ Depends on: COMMON_CLK [=y] &&&& OF [=y] &&&& (ARCH_ZYNQMP [=y] || COMPILE_TEST [=n])


Devicetree (for 2018.1 release)

For more details on clock bindings please refer "Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt"

clk: clk { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; };


Devicetree (for 2017.4 and earlier releases)

For more details on phy bindings please refer "Documentation/devicetree/bindings/clock/zynq_mpsoc.txt"


clkc: clkc@ff5e0020 { #clock-cells = <1>; compatible = "xlnx,zynqmp-clkc"; clocks = <&&pss_ref_clk>, <&&video_clk>, <&&pss_alt_ref_clk>, <&&aux_ref_clk>, <&&gt_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; clock-output-names = "iopll", "rpll", "apll", "dpll", "vpll", "iopll_to_fpd", "rpll_to_fpd", "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", "dbg_trace", "dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref", "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", "topsw_main", "topsw_lsbus", "gtgref0_ref", "lpd_switch", "lpd_lsbus", "usb0_bus_ref", "usb1_bus_ref", "usb3_dual_ref", "usb0", "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", "uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref", "adma_ref", "timestamp_ref", "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; };



Test Procedure

The following driver use cases is tested.
Mainly clock enable and disable on following drivers

  • i2c

  • qspi

  • sd card

  • nand

  • uart

  • gem

  • gpio

  • dma

  • sata

  • apm


Data rate change is tested with gem.
Sample expected log is below

root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 1000 duplex full root@Xilinx-ZCU102-2016_2:~# [ 1168.866072] macb ff0e0000.ethernet eth0: link down Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6050C00 Received IPI Mask:0x00000001 PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6010C00 Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00 [ 1170.890303] macb ff0e0000.ethernet eth0: link up (1000/Full)



root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 10 duplex full root@Xilinx-ZCU102-2016_2:~# [ 1192.898072] macb ff0e0000.ethernet eth0: link down Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00 Received IPI Mask:0x00000001 PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6320C00 Received IPI Mask:0x00000001 PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6320C00 [ 1195.922279] macb ff0e0000.ethernet eth0: link up (10/Full) root@Xilinx-ZCU102-2016_2:~#

Debug
View the Clock configuration summary.

cat /sys/kernel/debug/clk/clk_summary


Porting to CCF
Porting to CCF
Mainline status
Mainlined


Change log

2025.1

Summary:

  • drivers: clk: zynqmp: calculate closest mux rate

  • drivers: clk: zynqmp: update divider round rate logic

  • clk: zynqmp: add Versal Gen 2 compatible string

Commits:

2024.2

None

2024.1

None

2023.2

None

2023.1

Summary:

Commits:

2020.2

Summary:

  • clk: zynqmp: Handle divider specific read only flag

  • clk: zynqmp: Use firmware specific common clock flags

  • clk: zynqmp: Use firmware specific mux clock flags

  • clk: zynqmp: Add missing checking of eemi_ops

  • clk: zynqmp: Add a check for NULL pointer

  • clk: zynqmp: Make zynqmp_clk_get_max_divisor static

  • clk: zynqmp: make bestdiv unsigned

Commits:

2022.2

None

2022.1

Summary:

  • clk: zynqmp: Use firmware specific common clock flags

  • clk: zynqmp: Use firmware specific divider clock flags

  • clk: zynqmp: Use firmware specific mux clock flags

  • clk: zynqmp: Handle divider specific read only flag

  • clk: zynqmp: Fix kernel doc

  • clk: zynqmp: Fix a memory leak

Commits:

2021.2

Summary:

  • clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable

  • clk: zynqmp: divider: Align max_div description with mainline

  • clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback

  • clk: zynqmp: pll: Remove some dead code

  • clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected

  • clk: zynqmp: Sync with mainline

Commits:

2021.1

  • None

2020.1

Summary:

  • clk: zynqmp: Fix CLK_FRAC bit index

  • clk: zynqmp: Fix missing max_div description in kernel-doc format

  • clk: zynqmp: Fix divider2 calculation

  • clk: zynqmp: fix memory leak in zynqmp_register_clocks

  • drivers: clk: Fix invalid clock name queries


Commits:

2019.2

Summary:

  • clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag

  • clk: zynqmp: Recalculate bestdiv for DIV2 clock

  • clk: zynqmp: Warn user if clock user are more than allowed


Commits:



2019.1

Summary:

  • clk: zynqmp: Extend driver for versal

  • clk: zynqmp: fix doc of __zynqmp_clock_get_parents

  • clk: zynqmp: Add support for custom type flags

  • drivers: Defer probe if firmware is not ready


Commits:



2018.3

  • None

2018.2

  • None

2018.1
Summary:

  • Move MMIO error to debug from warn

  • Use SPDX license

  • Replace clock driver with new driver which fetches clock information from firmware


Commits:

2017.4
Summary:

  • Remove unused variables


Commits:
clk: zynqmp: Remove a unused variable



2017.3
Summary:

  • Fix the usb mux offset

  • Some waning fixes


Commits:
clkc: zynqmp: fix the usb mux
zynqmp: Use new firmware.h instead of pm.h
clk: zynqmp: divider: Fix the warnings
clk: zynqmp: Remove variables set but not used

2017.2
Summary:

  • In some cases the second divisor was was getting saturated resulting in some ethernet failures.this is fixed.


Commits:
clk: zynqmp: Let the frac be decided on the frac capability

2017.1
Summary:

  • The watchdog source is corrected.

  • Since for dp to work it changes the parent rate. We do not support dp sharing the parent (VPLL).A warn is added to check for the same.

  • Sets the set rate parent for video clocks.

  • Fractional mode support is enabled.


Commits:
clk: zynqmp: Fix the watchdog clock source
clk: zynqmp: Warn on vpll multiuser conditionally
pll: zynqmp: Add support for pll set rate
clk: zynqmp: Set the needed flags
clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks
clk: Reset the child count
clk: zynqmp: pll: Enable the fractional mode when needed
clk: zynqmp: Prevent un-necessary rounding off
clk: zynqmp: Enhance the prints

2016.4
Summary:

  • the GEM mux shift values are corrected.


Commits:
clk: zynqmp: Fix GEM mux shift values

2016.3
Summary:

  • Adds basic clock support for zynqmp.


Commits:
clk: zynqmp: Add initial ccf clkc support
clk: zynqmp: add mux changes for zynqmp
f5e303d clk: zynqmp: Add zynqmp divider support
8592671 clk: zynqmp: Add zynqmp ultrascale gate support
ea2cd726 clk: zynqmp: Add the pll driver
4d85a2c clk: zynqmp: Fix GEM mux shift values


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