Power Optimization Guide for Zynq UltraScale+ MPSoC

This guide covers techniques that can be applied to achieve low power consumption on Zynq UltraScale+ MPSoC based systems. All the phases of design are considered and techniques corresponding to each phase are discussed with appropriate references wherever applicable. Examples demonstrating most of the techniques are attached for users to try out and serve as references.

Table of Contents

Board Design Phase


Device Selection

Selecting a device of right capacity and speed grade can help minimize both static and dynamic power consumed by a device.

Device Capacity

Static power is directly proportional to device capacity. Programable Logic is the main consumer of power on a ZU+ device. There are different device variants available with variable PL capacity. So, selecting a device with minimal capacity that can fit the application is critical to minimizing the power consumed by PL.

For example, XCZU19EG device consumes 850mW more than a XCZU2EG device in static power.

Speed Grade

ZU+ devices are available in speed-grades that can work with the PL at lower voltages of 0.72V when compared to the nominal 0.85V devices. As discussed earlier, operating at a lower voltage helps in reducing both static and dynamic power consumption significantly. So, for applications having stringent power goals, these low power variants need to be considered.

For example, on a ZU7EV device, using a -2L device instead of a -2 device, and bringing down PL voltage to 0.72V, can save around 20% of total power consumption.

ZU+ devices are available in -1L and -2L grades which are low power variants of -1 and -2 speed grades respectively. Refer to Zynq UltraScale+ MPSoC product selection guide for more details.

Schematic Design

To achieve low power states involving turning off PL/FPD domains and features like board power off from software, there are certain guidelines that need to be followed. These are dealt in detail on the page: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1417183259 .

An optimized schematic design can sometimes save 15% more power by enabling a low power standby state, or by allowing a more aggressive PL Power Management design.

Impact of Capacitance on PL Power Management

PL Power Management includes simultaneously turning off/on the clocks for a clock domain. Please model this effect and increase the capacitance on VCCINT if required. Capacitors and switching loads are discussed in ug583 - UltraScale Architecture PCB Design User Guide, PCB Decoupling Capacitors.

GPIOs for PL Power Management Control

PL Power Management includes GPIO controls to clock managers so the PL clock domains can be frequency scaled or turned off. These are typically controlled externally to the PL by EMIO, AXI, or I2C. But they can also be controlled internally to the PL. Though the GPIOs are internal, the resources need to be reserved during the schematic design.


Vivado Design Phase

Once the board design is finalized and the actual development of platform starts in Vivado, there are several techniques that can be applied to lower the power consumption. Vivado design is split into PS and PL design phases and corresponding techniques are provided.

PS Design Optimizations

The PS side of the design optimizations to save power involves disabling unused blocks, optimizing clocks, DDR configurations, etc. The PS has power islands which can be power gated to eliminate static power consumed by that island. Power gating is handled by the PM framework automatically at runtime. See Linux Power Management section for details on runtime PM. The PM framework depends on the configuration specified in Vivado to power down unused blocks. So it is essential to properly specify which blocks are used/unused to get the power savings. It is typical to be able to save 20% of the PS power this way. Here is a list of techniques that can be applied to PS configuration:

  1. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1430192189

  2. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1417183678

PL Design Optimizations

Vivado Options for Power Optimization

For PL Designs, different implementation options are presented by Vivado including Optimization for Power. For designs targeting low power, this setting needs to be selected. It is typical to be able to save up to 30% of the PL power this way, depending on the design contents. Here is a snapshot of the selection in “Implementation Settings” dialog.

More detailed instructions are covered by these guides provide by Xilinx:



Clocks and Power Mode Controls

To enable runtime power management, there are several techniques that need to be employed in defining controls for clocks and power modes of PL IPs. These techniques are explained in detail on this page: . It is typical to be able to save 40% of the PL power this way.


Software Build & Runtime

The software stack used for each application may vary depending on the use-case. Xilinx supports runtime power management for Linux and bare-metal applications. All required drivers and libraries are available from Xilinx. Using these runtime PM features in software is critical to achieving lower power consumption. There is an example which demonstrates the typical power states that can be achieved using Xilinx provided software stack here:

Linux Power Management

Linux has built-in support for runtime PM and Xilinx provides the required drivers to make this work on Zynq UltraScale+ devices. Refer to this page for a detailed tutorial on Linux PM: .

CPU specific power management techniques are discussed in more details on this page: .

Bare-Metal Apps using XilPM Library

For applications using XilPM standalone library, refer to UG1199 for detailed guidance on using XilPM for power management.

Custom Software Stack

For applications which use a custom software stack which cannot leverage Xilinx provided power management framework or not interested in active runtime power management, but still looking for an efficient low power design, here are a few techniques that might be useful:


Debugging Power Management Issues

There may be a need to debug or explore the power, clock and reset states of various blocks on the SoC. In such scenarios, this page might be helpful: .


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