This page describes various power optimization techniques that can be applied to a Zynq UltraScale+ MPSoC VCU based design.

Table of Contents

Clock Configuration

Video Codec Unit (VCU) has encoders and decoders which can be independently clock gated. There is a VCU PLL which provides clocks for the encoder, decoder and MCUs. When the VCU is not used, it can be clock gated and PLL shutdown to save power. This is best achieved by unloading the VCU driver and loading it only when required.

To minimize the dynamic power consumed by VCU, it is critical to select a minimum operating frequency that helps in achieving desired resolution, no. of streams and FPS. The frequency selection can be made in VCU IP config dialog in Vivado. For calculation of the optimal clock frequency, refer to VCU Programmers Guide.

Here is a screenshot of VCU IP configuration in Vivado to setup Clock frequency that impacts power:

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Encoder/Decoder Settings

Choosing the minimal required settings for encoder/decoder is critical for power optimization since this will impact the buffer sizes.

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In cases where only encoder is required, the decoder can be disabled to save power and vice versa.

Related Links

• https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/pg252-vcu.pdf