Interconnects are the highways for data flow within the SoC and are generally clocked at higher frequency ranges to derive the best performance possible. However, this may lead to situations where the interconnect has a lot of spare bandwidth and thus leading to unnecessary power drain. To optimize the power consumed, it is important to select the minimum required frequency depending on bandwidth requirements for the application.
Deciding on an optimal interconnect clock frequency is critical since both performance and power need to be balanced. Refer to “PS Interconnect” section in TRM and Wiki for details on various interconnect paths and performance modelling.
Configuring Interconnect Frequency
PM framework considers interconnect clocks as system clocks since they impact the functionality of the entire system including PMU. So, the control for changing these clocks at runtime is blocked by PMUFW. Interconnect clock frequency is configurable at design time in PCW. In ZU+, the interconnect clocks in both LPD and FPD can be configured depending on the bandwidth requirements for the application.
Here is a screen shot of Interconnect clock settings in PCW:
Dynamic power consumed by interconnect is directly proportional to the clock frequency. For example, scaling down the TOPSW_MAIN clock in FPD by half from 533MHz to 266MHz brings down the power by around 100mW. So, selecting an optimal interconnect clock frequency can provide significant power savings.