DDR Power Optimization

This page discusses the techniques that can be used to optimize the power consumed by DDR controller and related Vivado options available.

Table of Contents


DDR is one of the highest power-hungry blocks on the SoC. So, there is a lot of room for reducing power consumption of DDR controller. There are two parameters which can be tuned at design phase to reduce DDR Power. But these should be carefully tuned based on the data transfer bandwidth requirements for the application.

DDR Clock Frequency

ZU+ DDR controller supports operating at a wide range of frequencies and thus provides an opportunity to select the minimal operating frequency for a given application. This frequency selection directly affects the power consumption.

DDR Bus Width

Using a lower bus width is known to reduce the power consumption, but it also reducing the addressable memory range. So, depending on the application, the lowest bus width which fits in should be selected to minimize power consumption.

Clock Stop

When this feature is enabled, the DDR PHY is allowed to stop the clocks going to the DRAM. For DDR2 and DDR3, this feature is only effective in self-refresh mode. For LPDDR and LPDDR2, this feature becomes effective in Idle periods, Power-down mode, Self-refresh mode, and Deep power-down mode.

Pre-charge Power Down

When enabled, the DDRC dynamically uses pre-charge power down mode to reduce power consumption during idle periods. Normal operation continues when a new request is received by the controller.


© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy