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Zynq UltraScale+ FSBL

Zynq UltraScale+ FSBL

This page  provides details on building and customizing the FSBL for Zynq UltraScale+ MPSoC, and important notes on the FSBL. All the information is presented in the format of FAQs.

Table of Contents

What is FSBL?


First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each partition can be a code image or a bitstream. Each of these partitions, if required, will be authenticated and/or decrypted.
FSBL is loaded into OCM and handed off by CSU BootROM after authenticating and/or decrypting (as required) FSBL.

How to create FSBL from Vitis?

  • Launch VITIS with the below command: vitis
  • Provide path where VITIS workspace and project need to be created. With this VITIS workspace will be created
  • (Optional step) To work with local repos, Select "Xilinx" (ALT - x) -> Repositories. Against Local Repositories, click on "New..." and provide path of the local repo
  • Select File-->New-->Application Project to open "New Project" window, provide name for FSBL project
  • In the “Platform” section, click on “Create a new platform from hardware (XSA)” and select pre-defined hardware platform for ZynqMP (e.g. zcu102).
    • Alternatively, to create a new/custom platform from a .xsa file, click on “+”, browse and select the XSA file and a new hardware platform is created.
  • In the "Domain" window, select the processor psu_cortexa53_0/psu_cortexr5_0, OS as standalone and Language as C
  • Click Next and select "Zynq MP FSBL"
  • Click "Finish" to generate the A53/R5 FSBL. This populates the FSBL code and also builds it (along with BSP)
  • Debug prints in FSBL are now disabled by default (except for FSBL banner). To enable debug prints, define symbol: FSBL_DEBUG_INFO
    • In VITIS this can be done by: right click on FSBL application project -> select “C/C++ Build Settings” -> “Tool Settings” tab -> Symbols (under ARM v8 gcc compiler)
    • Click on Add (+) icon and Enter Value: FSBL_DEBUG_INFO, click on "OK" to close the "Enter Value" screen
  • In case any of the source files (FSBL or BSP) need to be modified, browse the file, make the change and save the file, build the project. elf file will be present in the Debug/Release folder of FSBL project.

What are various levels of debug prints in FSBL?

FSBL supports four levels of debug prints:
Type or printsPurposeEnabled by defining.. in FSBL codeAlternative way of enabling by defining symbol..
ALWAYSUsed for prints, which should be always enabled (e.g. FSBL banner)