This page focuses on Ethernet-based designs that use Zynq® UltraScale+™ devices. It describes the use of the gigabit Ethernet controller (GEM) available in the processing system (PS) through the extended multiplexed I/O (EMIO) and multiplexed I/O (MIO) interfaces. It also describes the use of 1000BASE-X, SGMII, and 10GBASE-R physical interfaces using high-speed transceivers in programmable logic (PL). The use of Ethernet jumbo frames in both PS and PL-based Ethernet systems is explained in this application note. Throughput numbers for PS Ethernet, PL Ethernet (1G and 10G), and PS-PL Ethernet are also included. The designs explained in this application note demonstrate Ethernet solutions with kernel-mode Linux device drivers.

Download the reference design files for this application note from the corresponding github repository:

ZCU102

Table of Contents

Introduction

Zynq UltraScale+ devices integrate a flagship ARM® Cortex®-A53 64-bit quad-core or dual-core processor, Cortex-R5 dual-core real-time processor in PS, and PL in a single device. The PL includes the programmable logic, configuration logic, and associated embedded functions. The PS comprises the ARM Cortex-A53 MPCore CPUs unit, Cortex-R5 processors, on-chip memory, external memory interfaces, cache coherent interconnect (CCI), and peripheral connectivity interfaces. The PS is equipped with four GEMs. Each controller can be configured independently and uses a reduced gigabit media independent interface (RGMII). The RGMII interface is routed through MIO pins to interface with an external RGMII PHY. Other Ethernet communications interfaces such as TBI, RGMII v2.0, and SGMII can be created in the PL using the GMII/MII available on the EMIO interface. SGMII is also supported by the GEM using the PS-GTR transceiver without using any logic in the PL. Figure 1 shows the various Ethernet implementations on the ZCU102 board.

Open

Figure 1: Zynq UltraScale+ MPSoC Ethernet Interface

Note: The PS-GEM3 is always tied to the TI RGMII PHY on the ZCU102 evaluation board. The 1000BASE-X/SGMII PHY and the GTH transceiver are a part of the AXI Ethernet core for 1G PL Ethernet link, which uses the AXI 1G/2.5G Ethernet subsystem IP core [Ref 1]. The PS-PL Ethernet uses PS-GEM0 and 1G/2.5G Ethernet PCS/PMA, or SGMII core [Ref 2]. The 10G PL Ethernet link uses 10/25G high-speed Ethernet subsystem IP core [Ref 3].

In the designs provided with this application note, the PS-GEM3 is connected to the Texas Instruments DP83867IRPAP Ethernet RGMII PHY device through the reduced gigabit media independent interface (RGMII). This is the default setup for the ZCU102 board. This application note demonstrates various PS and PL-based Ethernet implementations. The designs described in this application note are listed below.

• PS Ethernet (GEM3) connected to a 1G physical interface in PS through an MIO interface. See Using PS GEM through MIO.

• PS Ethernet (GEM0) connected to a 1000BASE-X/SGMII physical interface in PL through an EMIO interface. See Using PS GEM through EMIO.

• Ethernet implemented as soft logic in PL (MAC) and connected to the 1000BASE-X/SGMII physical interface in PL. See Using PL 1G Ethernet.

• Ethernet implemented as soft logic in PL (MAC) and connected to the 10G physical interface in PL. See Using PL 10G Ethernet.

Note: GEM0, GEM1, or GEM2 can also be used for PS Ethernet. The hardware design varies depending on the GEM selected.

Using PS GEM through MIO

This section describes how to use the PS Ethernet block GEM3 with the PS PHY through the MIO interface.

Hardware Design

The PS Ethernet controller (GEM3) connects the on-board TI PHY through MIO pins using the RGMII interface. The GEM3 block is enabled while generating the hardware system. The GEM3-TI PHY link is shown in Figure 1 with the PS-GEM3 link. For more information refer to the PS and PL based Ethernet in Zynq MPSoC wiki [Ref 4].

Reference Clock Generation

The Ethernet reference clock (125 MHz) for each of the GEMs is generated by configuring the internal PLL of the PS.

Software Design

This design uses the common macb.c driver code (present in the Linux kernel) for all the GEMs on the ZCU102. The macb driver uses the direct memory access (DMA) controller attached to the GEM in the PS. This driver is responsible for several functions including DMA descriptor rings setup, allocation, and recycling. The interrupt handling is done only for the PS GEM events because the interrupt status implicitly reflects DMA events. Additionally, the device tree is updated to include PS-GEM3 with relevant parameters. Refer to Device Trees for more information.

Linux Driver

A monolithic Linux device driver is used in this design. The software architecture for PS Ethernet interfaces is shown in Figure 2.

Open

Figure 2: PS Ethernet Software Driver for Linux

Using PS GEM through EMIO

This section describes the use of the PS Ethernet block GEM0 with the PL PHY through the EMIO interface. The PS GEM block can be accessed through the PL using EMIO pins that allow GMII and management data input/output (MDIO) interfaces to be connected to the physical layer. The 1G/2.5G Ethernet PCS/PMA or SGMII core can be used as the physical media for the Ethernet in 1000BASE-X or SGMII mode. High-speed serial transceivers are used to access the small form factor pluggable (SFP) cage on the ZCU102 board. The SFP cage is connected to a standard Ethernet LAN through an SFP-to-RJ45 converter module. To enable the SFP, jumper J16 should be shorted as shown in Figure 7.