Board Design Considerations for Power Management
Power Management starts at board design level since the knobs to control power rails are decided by the board design. In this guide we cover specific PM related design guidelines that need to be considered to enable proper runtime power management. For a general guidance on power supply selection and other aspects of board design, please refer to the TRM and other guides available on Xilinx Website.
Table of Contents
Introduction
It is a general practice to group multiple rails into a single power supply source to optimize overall cost of the board or control IOs. But for applications requiring fine grain power control and use-cases where certain power domains can be powered-off for significant durations, it is essential to have independent power supply controls for LPD, FPD and PLD.
Power Rail Control
PM Framework enables runtime control of power supplies using MIOs. These controls can be used to power up/down PL, FPD and LPD (whole chip). If the end application needs to realize power states that involve powering ON/OFF PL and FPD domains, then the board should be designed to connect the respective MIOs to power supply controller as described in the table below:
MIO | PMU GPO | Power Domain |
|---|---|---|
MIO 32 | GPO1[0] | FPD |
MIO 33 | GPO1[1] | PLD |
MIO 34 | GPO1[2] | Software defined, but in general used for full chip or board power down |
Note that these MIOs will be tri-stated during power up and booting. So, a strong pull-up should be provided on the board to keep the power ON as default state during startup.
PMUFW Config for Board Power Down
PMUFW supports board power down use-cases where software running on APU/RPU can request for a full shutdown of the board. A common example of such usage is the case where running “shutdown” command in Linux powers down the board. To enable this functionality, the following PMUFW build flags need to be enabled:
BOARD_SHUTDOWN_PIN=2
BOARD_SHUTDOWN_PIN_STATE=0
To setup PMUFW build flags in PetaLinux, use “petalinux-config” command and then select “PMUFW Configuration” -> “PMUFW Compiler Flags” and set the value as shown in figure below:
Note that the board needs to be designed to use the specified MIO (in this case MIO34) as board power kill signal to the power supply controller. Though any of the PMU GPOs can be used for this purpose, it is recommended to use MIO34 (PMU GPO1[2]).
This feature works only on boards like ZCU102 that have a provision to shutdown the board using a dedicated MIO, and is not a generalized solution. So, generally for boards that don't have this board feature, Deep Sleep is the viable solution recommended instead at 35mW, but this one is worth keeping in mind.
Related Links
© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy