In this simple demo, we will learn how we can use theJTAG to AXIto peek and poke registers of IP in the PS and the PL. I will be using the ZCU102 board. However, this would apply for any Zynq ultrascale device.
We will also discuss how we can use this feature in a TCL script in order to automate testing.
Table of Contents
Here, I have added the JTAG to AXI IP from the IP catalog and have connected this master to the AXI GPIO, and to the slave port on the PS. The Address map for the JTAG to AXI master is seen below:
Note: I am using the Clock and Reset from the Zynq PSU block for the IP in the PL. I used the board settings for the ZCU102 and made slight changes to enable the slave ports, and disabled the master ports.
I will use the FSBL to config the PSU. The FSBL will also toggle the PS to PL reset.
Since I need to configure the PSU. I will export to SDK, and create an FSBL. I then used the create boot image GUI to create the BOOT.BIN file that contains the bitstream and the fsbl.elf.
Place the BOOT.BIN onto an SD Card, and boot:
Connecting to Vivado Hardware Manager:
In Vivado, select Open Hardware Manager → Open New Target → Open New Target → Next
Note: If you are doing a remote connection, then make sure you have ahw_managerrunning on the local machine, and add relevant info into the Hardware Sever Settings GUI
Note: this can also be done via the TCL console:
If connection is successful you should see the following (where the highlighted is the jtag to axi instance):
Poking IP over JTAG to AXI IP:
To do a simple poke of a register, the user can follow the examples on page 19 in the linkhere. For example, lets turn on the LED: