Optimizing Peripheral Clock Frequencies

This page describes the methods to optimize clock frequencies for peripherals to minimize power consumption.

Table of Contents


Clock rate directly contributes to dynamic power dissipation. The clock frequency set selection for a design should be made to keep them at the minimal required ranges for meeting the specifications. These are design time decisions that need to be made considering the specific performance metrics for that design.

Optimize Clock Frequencies at Design Phase

Clock frequencies for all peripherals, processors and interconnects can be configured in the PCW wizard. In general, presets in the default designs provided may have clocks configured to the highest frequency rated for the block. Scrubbing through this list and reducing the frequencies as required by the application will greatly improve the power numbers.

Here is a screen shot of PCW wizard where peripheral and processor clock frequencies can be configured:

Runtime Clock Control

Once design time optimizations are done to minimize the clock frequencies for all peripherals, cores and interconnects, further power savings can be achieved by utilizing runtime clock gating/scaling techniques. For this purpose, EEMI provides clock management APIs:

  1. Clock Get State

  2. Clock Enable

  3. Clock Disable

  4. Clock Get Divider

  5. Clock Set Divider

In Linux, Common Clock Framework (CCF) automatically manages the clocks at runtime without user intervention. Clocks related to unused blocks are automatically gated by the framework. Baremetal applications can use the above mentioned EEMI APIs to implement clock controls.  For applications that don’t use PM Framework, boot time clock gating of unused blocks can be considered to extract some level of power savings.

Related Links


© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy