Xilinx DRM KMS DisplayPort 1.4 TX Subsystem Driver

The purpose of this page is to describe the Linux DRM driver for the Xilinx DisplayPort 1.4 Tx Subsystem Soft IP for the Zynq UltraScale+ MPSoC.

Table of Contents


The purpose of this page is to describe the Linux DRM driver for Xilinx DisplayPort 1.4 TX Subsystem Soft IP for Zynq Ultrascale+ MPSoC.

The DisplayPort 1.4 Tx Subsystem implements functionality of a video source as defined by the Video Electronics Standards Association (VESA)'s DisplayPort standard v1.4 and supports driving resolutions of up to Full Ultra HD (FUHD) at 30 fps. The subsystem is a hierarchical IP that bundles a collection of DP TX-related IP sub-cores and outputs them as a single IP. The subsystem takes incoming video stream and transfers them to an DP stream. The stream is then forwarded to the video PHY layer. Below is the block diagram of DisplayPort 1.4 Tx Subsystem.

DisplayPort Tx Subsystem Block Diagram

Figure 1. Block diagram of DisplayPort 1.4 Tx Subsystem

The DP 1.4 Tx Subsystem is a MAC subsystem which works with a Video PHY Controller (PHY) to create a video connectivity system. The DP 1.4 Tx Subsystem is tightly coupled with the Xilinx Video PHY Controller, which itself is independent and offer flexible architecture with multiple-protocol support. Both MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Figure 2. Block diagram of MAC Interface with PHY

Driver Overview

DP Tx is the last node in the display pipeline. The Linux driver is implemented as a sub-component of the Xilinx DRM KMS bridge driver (bridge driver name : xlnx) and implements the encoder/connector interface. The subsystem includes the video timing generator and Tx sub-core. Driver implements the DRM callbacks to read the display EDID and present it to the framework anytime a display is connected. It works in tandem with the DRM bridge driver to validates each mode listed in the EDID and reject unsupported modes.

On mode change request from user application driver works in conjunction with DRM framework to validate the requested mode to ensure the stream can be generated by Tx core and is supported by the attached display. If requested mode is supported, the driver will configure Tx sub-core for new mode ,the internal video timing controller (VTC) to generate requisite video timing for it .It also configures the PHY layer for the new mode and manages all required interaction between MAC & PHY layer.

After mode setup is complete PHY state machine is reset and put into a wait state awaiting the reference clock for the new mode from an external clock source. DRM framework requests the registered clock producer  to generate the clock for desired mode. 

IP/Driver Features

IP Feature2020.12020.2
IP Version Supported2.13.0
Supports AXI4-Stream, native video input interfacesAxi-Stream Video OnlyAxi-Stream Video Only
Support for 2 pixel per sampleYesYes

Support color space for RGB, YUV 4:4:4, YUV 4:2:2,Y-only 

Audio support for 2 to 8 channelstYesYes
8, 10, 12, and 16-bit Deep-color support8 and 10-bit only 8 and 10-bit only 
Support for 16-bit GT width.YesYes
Support HDCP 2.xNoNo
HDCP in MST mode NoNo
In-band stereoNoNo
Video AXI4-Stream interface is not scalable with dynamic pixel mode selectionNoNo
Dual-pixel splitter in native video modeNoNo
Supported resolution up to 8k30YesYes
Supported interlaced mode NoNo

Missing Features / Known Issues / Limitations in Driver

  • This driver does't support following features 
    • HDCP 
    • Audio

Kernel Configuration Options for Driver

2019.2 and onwards: Supports ONLY the new Xilinx DRM framework driver and PL crtc and can be enabled via following configurations options CONFIG_DRM_XLNX and CONFIG_DRM_XLNX_PL_DISP

The above defined options will only enable the new DRM framework. Since DP Tx driver is now added as an out-of-tree kernel module, there is no kernel configuration required.

Building Driver Modules 

  • run the below command to build the kernel

    • $ make kernel
  • run the below command to build the dp-modules 
    • $make modules
  • Insert the above built modules after the kernel boots up, insert them in  a sequence as shown below 
    • insmod phy-xilinx-vphy.ko

    • insmod xilinx_dp.ko

  • Now the DP Tx driver is ready to use.

Device Tree Binding

The dts node should be defined with correct hardware configuration. An example device tree node is documented in

2020.1: Documentation/devicetree/bindings/xlnx,v-dp-tx-ss.txt

2020.2: Documentation/devicetree/bindings/xlnx,dp-tx.yaml

Example Design Architecture 

Figure 3. DisplayPort Tx example design architecture 

Test Procedure

DP-Tx can be manually configured to generate the required mode. An open source utility like modetest can be used to configure the display pipeline.

  • DDR ==>FB_Rd (DMA)==>DP _Tx

2020.1 and on wards Sample command to set a mode is shown below

example command 

Above command will generate a color bar pattern at requested resolution in DDR, configures the DMA to read the frame from DDR and configures the DP Tx for said resolution. As a final result Color Bar at defined resolution should be visible on screen.

Driver also supports changing output color formats dynamically. Available output color formats supported by DMA engine can be determined using modetest utility as shown below

Refer Line "formats"that indicates the FrameBuffer DMA IP configuration supports XB30 VU24 XV30 YUYV XV20 BG24 GREY Y10 color formats. This setting is configured by the DMA driver device tree node property xlnx,vid-formats 

Debug Capability

 DP Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer

Boards Supported

Driver has been tested on following boards

  • zcu102 Rev-D
  • zcu102 Rev 1.0

Change Log

  • 2020.2

    • Summary:
      • Removed the support for external AXI Remapper 

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