Page overview: This page describes the Linux DRM driver for the AMD/Xilinx MIPI DSI-2 Transmitter Subsystem, including supported IP/driver features, kernel configuration, device tree binding, validation procedure, tested boards, known issues, change history, and related references. It is aligned with the MIPI DSI-2 Transmitter Subsystem Product Guide (PG238) and the current linux-xlnx DSI TX driver.

Introduction

The MIPI DSI-2 Transmitter Subsystem implements a transmit interface for MIPI DSI display pipelines. It receives AXI4-Stream video data, inserts the required DSI protocol markers such as hsync start and hsync end, frames DSI packets according to the configured video mode and data format, and sends the packetized stream to a MIPI DSI-compliant display panel through the selected PHY interface.

The subsystem supports MIPI DSI standard v2.0 Type 4 architecture with MIPI D-PHY v2.0 or MIPI C-PHY v2.0 physical-layer options, depending on the selected IP configuration, device family, and platform. PG238 documents the complete IP feature set, line-rate limits, PHY options, data types, resource utilization, and configuration details.

This page documents only the Linux DRM KMS driver for the AMD/Xilinx MIPI DSI-2 TX Subsystem soft IP. The driver source is xlnx_dsi.c. It is part of the Xilinx DRM KMS framework and provides DSI encoder and connector functionality for display pipelines that typically include framebuffer read or video mixer IP upstream and a DRM panel driver downstream.

The Linux driver programs the DSI TX registers using the AXI4-Lite interface described by the device tree, exposes DRM connector properties for supported runtime controls, and relies on the connected panel driver and display pipeline to provide the mode timing, input format, and stream enable sequence.

IP / Driver Features

IP Features	2017.1 - 2019.1	2019.2 and above till 2026.1

IP Features	2017.1 - 2019.1	2019.2 and above till 2026.1
IP Version	2.0	2.0
Compatible string	`xlnx,dsi`	`xlnx,dsi`
Support for one to four D-PHY lanes and one to three C-PHY lanes	D-PHY supported by the Linux driver	D-PHY supported by the Linux driver. C-PHY is an IP/PG238 capability; Linux driver validation is not documented on this page.
Line rate support	Supported by IP. Refer to PG238 and device datasheet for exact limits.	PG238 lists 260–2500 Mb/s for Versal adaptive SoCs, 80–2500 Mb/s for other supported devices, and Gen 2 device limits for D-PHY/C-PHY. Linux driver uses the fixed clock configuration from device tree.
Input pixels per clock 1 / 2 / 4	Yes	Yes
DSI data types: RGB888, RGB565, RGB666 loosely packed, RGB666 packed, Compressed	Supports all except Compressed. Compressed video data type is not supported through the current DRM pipeline.	Supports all except Compressed. Compressed video data type is not supported through the current DRM pipeline.
Fixed Virtual Channel Identifier (VC) 0	Yes	Yes
Internal D-PHY/C-PHY direct connection to a DSI-compliant display panel	Internal D-PHY	Internal D-PHY in validated Linux designs; C-PHY depends on IP/platform configuration and driver validation.
AXI4-Lite interface for register access	Yes; required by the Linux driver	Yes; required by the Linux driver
AXI4-Stream input compliant with UG934	Yes	Yes
Pixel-to-byte conversion based on data format	Yes; handled by IP according to configured data format	Yes; handled by IP according to configured data format
Programmable EoTp generation support	Yes; exposed as DRM connector property	Yes; exposed as DRM connector property
ECC generation for packet header	Yes; IP generated	Yes; IP generated
CRC generation for data bytes	Optional IP feature; configured in hardware	Optional IP feature; configured in hardware
Blanking packet / LP mode controls for BLLP periods	Yes; DRM connector properties are available	Yes; DRM connector properties are available
Video mode transmission sequence and burst payload configuration	Yes; supported through driver properties and mode configuration	Yes; supported through driver properties and mode configuration
DCS (Display Command Set) command mode	No	Yes; short command support from 2019.2 and generic long write support from 2020.2
Interrupt generation to indicate subsystem status information	IP supports interrupts, but Linux driver does not support interrupt handling.	IP supports interrupts, but Linux driver does not support interrupt handling.

Other supported features

The MIPI DSI-2 Tx Subsystem driver supports the following features -

Enable or disable EoTp generation.
Send blanking packets or use LP mode for BLLP periods.
Configure blanking packet type for the BLLP region.
Select blanking packet or null packet behavior.
Configure the video mode transmission sequence.
Configure BLLP duration of the VACT region packet.
Configure payload size in bytes (WC), applicable only for burst mode.
Write short and long command packets to control the panel when DCS command mode is supported. Refer to PG238 for DSI command details.

Missing Features / Known Issues / Limitations in Driver

Reading DSI panel parameters from EDID is not supported. Panel timing must be provided by the panel driver/device tree.
Interrupt handling is not supported in the Linux driver, although the IP can generate interrupts for subsystem status.
C-PHY is documented as a PG238 IP capability, but this Linux driver page does not document a validated C-PHY Linux design.
Compressed DSI data type is an IP capability, but it is not supported through the current DRM pipeline documented here.
DCS commands that require bi-directional MIPI I/O, including Bus Turn Around (BTA), are not supported.
Optional DSI sub-link features are not supported.
Non-continuous clock mode is not supported.
Dynamic line-rate change is not supported. The Linux driver uses the clock and line-rate configuration provided by the hardware design and device tree.
LPDT and ULPS escape mode support is not documented for this Linux driver.
Power suspend and resume flows are not documented as validated for this driver.

Build and Enable the Driver

Enable the following kernel configuration options for the Xilinx DRM framework and MIPI DSI-2 TX driver. The driver also depends on the DRM core, common clock framework, and a panel driver that supplies the display mode information.

CONFIG_DRM
CONFIG_DRM_XLNX
CONFIG_DRM_XLNX_DSI
CONFIG_DRM_PANEL_SIMPLE

Device Tree Binding and Example Pipeline

Device tree binding

The MIPI DSI-2 TX Subsystem node must match the hardware configuration generated by Vivado. The device tree describes the compatible string, register range, clocks, reset and panel connections, data-lane configuration, video mode configuration, and DRM graph endpoints.

Use the binding file as the source of truth for required and optional properties: xlnx,dsi.yaml.

In a complete display pipeline, the DSI TX input endpoint must be connected to the upstream display pipeline component, such as Video Mixer or Framebuffer Read, using matching graph endpoints. The DSI TX output is connected to the panel node handled by the appropriate DRM panel driver.

Example validation pipeline

The driver has been validated as part of a display path that sends RGB video to a MIPI DSI display panel. A common validation pipeline is:

IMX274 Sensor → MIPI CSI-2 RX Subsystem → Video Processing → FRMBUF_WR -> DDR -> FRMBF_RD → MIPI DSI TX

The MIPI DSI-2 TX Subsystem contains the following major sub-cores:

Sub-Core	Function

Sub-Core	Function
MIPI D-PHY / C-PHY	Physical layer interface that transmits serial MIPI data to the display panel.
DSI TX Controller	Protocol layer that frames DSI packets, handles the fixed virtual channel, inserts sync markers such as hsync start and hsync end, and manages EoTp, ECC, and CRC generation based on subsystem configuration.
Pixel-to-Byte Converter	Converts incoming AXI4-Stream pixel data to byte-oriented DSI packet payloads based on the configured data format and pixels-per-clock setting.

Test Procedure

This procedure validates the MIPI DSI-2 TX display path using a 1920x1200 RGB888 panel with four D-PHY lanes and two pixels per clock, along with Framebuffer Read and Video Mixer IP.

Before running the commands, confirm that the DRM device, connector ID, CRTC ID, supported formats, and mode names match your board. Use modetest -M xlnx to inspect the DRM objects and update the connector ID and format in the commands if your generated design uses different values.

Inspect the DRM display pipeline

root@xilinx-zcu102-2019_1:~# modetest -M xlnx
Encoders:
id      crtc    type    possible crtcs  possible clones
30      29      DSI     0x00000001      0x00000000

Connectors:
id      encoder status          name            size (mm)       modes   encoders
31      30      connected       DSI-1           108x272         1       30
  modes: name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
  1920x1200 60 1920 2105 2105 3030 1200 1203 1208 1212 154500 flags: ; type: preferred, driver
  props:
        1 EDID:
                flags: immutable blob
                blobs:

                value:
        2 DPMS:
                flags: enum
                enums: On=0 Standby=1 Suspend=2 Off=3
                value: 0
        5 link-status:
                flags: enum
                enums: Good=0 Bad=1
                value: 0
        6 non-desktop:
                flags: immutable range
                values: 0 1
                value: 0
        19 CRTC_ID:
                flags: object
                value: 29
        32 eotp:
                flags: range
                values: 0 1
                value: 0
        33 video_mode:
                flags: range
                values: 0 2
                value: 0
        36 bllp_burst_time:
                flags: range
                values: 0 65535
                value: 0
        34 bllp_mode:
                flags: range
                values: 0 1
                value: 0
        35 bllp_type:
                flags: range
                values: 0 1
                value: 0
        37 cmd_queue:
                flags: range
                values: 0 16777215
                value: 0
        38 height_out:
                flags: range
                values: 2 4096
                value: 0
        39 width_out:
                flags: range
                values: 2 4096
                value: 0
        40 in_fmt:
                flags: range
                values: 0 16384
                value: 0
        41 out_fmt:
                flags: range
                values: 0 16384
                value: 0

CRTCs:
id      fb      pos     size
29      44      (0,0)   (1920x1200)
  1920x1200 60 1920 2105 2105 3030 1200 1203 1208 1212 154500 flags: ; type: preferred, driver
  props:
        20 ACTIVE:
                flags: range
                values: 0 1
                value: 1
        21 MODE_ID:
                flags: blob
                blobs:

                value:
                        845b0200800739083908d60b0000b004
                        b304b804bc0400003c00000000000000
                        48000000313932307831323030000000
                        00000000000000000000000000000000
                        00000000
        18 OUT_FENCE_PTR:
                flags: range
                values: 0 18446744073709551615
                value: 0

Planes:
id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
28      29      44      0,0             0,0     0               0x00000001
  formats: XB24 XR24 BG24 RG24
  props:
        7 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
        16 FB_ID:
                flags: object
                value: 44
        17 IN_FENCE_FD:
                flags: signed range
                values: -1 2147483647
                value: -1
        19 CRTC_ID:
                flags: object
                value: 29
        12 CRTC_X:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        13 CRTC_Y:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        14 CRTC_W:
                flags: range
                values: 0 2147483647
                value: 1920
        15 CRTC_H:
                flags: range
                values: 0 2147483647
                value: 1200
        8 SRC_X:
                flags: range
                values: 0 4294967295
                value: 0
        9 SRC_Y:
                flags: range
                values: 0 4294967295
                value: 0
        10 SRC_W:
                flags: range
                values: 0 4294967295
                value: 125829120
        11 SRC_H:
                flags: range
                values: 0 4294967295
                value: 78643200

Frame buffers:
id      size    pitch

root@xilinx-zcu102-2019_1:~#
root@xilinx-zcu102-2019_1:~# modetest -M xlnx -s 31:1920x1200@BG24 -w 31:video_mode:1
setting mode 1920x1200-60Hz@BG24 on connectors 31, crtc 29

root@xilinx-zcu102-2019_1:~#
root@xilinx-zcu102-2019_1:~# modetest -M xlnx -s 31:1920x1200@RG24 -w 31:video_mode:1
setting mode 1920x1200-60Hz@RG24 on connectors 31, crtc 29

root@xilinx-zcu102-2019_1:~#

Run display test with modetest

After identifying the connector ID and supported mode, use modetest to set the display mode and update connector properties such as video_mode. The examples below use connector 31 and the 1920x1200 mode shown in the inspection output. Adjust the connector ID, mode, and pixel format for your board.

modetest -M xlnx -s 31:1920x1200@BG24 -w 31:video_mode:1
modetest -M xlnx -s 31:1920x1200@RG24 -w 31:video_mode:1

Performance

Performance, line-rate limits, maximum resolution, frame-rate capability, and resource utilization depend on the selected device family, PHY mode, number of D-PHY lanes or C-PHY trios, pixels-per-clock configuration, data type, and Vivado timing closure. Refer to PG238 for the authoritative IP performance and utilization data. The Linux driver uses the fixed clock and hardware configuration described in the device tree; it does not perform runtime line-rate scaling.

Xorg (X11) and Mali GPU

The MIPI DSI-2 Tx Subsystem can be used with Xorg and the Zynq UltraScale+ MPSoC Mali400 GPU.

Since Xorg works with AR24 DRM format (DRM_FORMAT_ARGB8888), please ensure that this is enabled/supported in Video Framebuffer Read / Video_Mixer IP connected.

A user should enable the following packages in the PetaLinux Configuration to enable and test the GPU (Zynq™ UltraScale+™ MPSoC - Graphics Driver Stack - Mali 400) acceleration:

-> Filesystem Package -> libs -> libmali-xlnx -> Filesystem Package -> misc -> xf86-video-armsoc -> Filesystem Package -> x11 -> base -> xserver-org -> xserver-xorg-extension-glx -> Filesystem Package -> x11 -> mesa-demos

Steps to manually launch Xorg

Xorg &

Xorg clients look for the env variable to find corresponding server. Thus export before running clients from serial console.

export DISPLAY=:0.0

Run OpenGL ES test applications.

es2tri
es2gears_x11

Disable Xorg Timeouts:

The default settings for Xorg may cause the screen to go black after a 10 minute timeout. The user can disable these in their xorg.conf file using the following.

Section "Monitor"
        Identifier      "MIPI"
        Option          "DPMS"                  "false"
EndSection

Section "ServerFlags"
        Option "BlankTime"   "0"
        Option "StandbyTime" "0"
        Option "SuspendTime" "0"
        Option "OffTime"     "0"
EndSection

xset can be used to change some settings. The following can be used to change the power sate and force display on if a timeout occurs.

sleep 1; xset dpms force on  #Sleep adds a delay to help X from getting confused on the order of events
sleep 1; xset dmps force off

Power & Clock Management

There is no power down for the MIPI DSI IP. However the MIPI DSI IP clocks can be controlled using the Common Clock Framework.

Boards Supported

ZCU102 Rev 1.0

Platform note: PG238 documents broader device-family support for the MIPI DSI-2 TX Subsystem, including newer AMD adaptive SoC platforms depending on IP version, PHY selection, and device support. This Linux driver page lists only boards that have been validated with this DRM KMS driver and display pipeline.

Known Issues

MIPI DSI-2 Transmitter Subsystem Product Guide (PG238) — refer to the current AMD documentation for IP release notes and known issues.
AR66769 — legacy MIPI DSI TX Subsystem release notes and known issues for Vivado 2016.1 and later versions.

Change log

2026.1

No changes

2025.2

drm: xlnx: dsi: Fix the DSI timing calculation

2025.1

No changes

2024.2

No changes

2024.1

No changes

2023.2

No changes

2023.1

bf7fbee xilinx: Convert MODULE_LICENSE GPL v2 to GPL

2022.2

No changes

2022.1

no changes

2021.2

no changes

2021.1

no changes

2020.2

Summary
- Added support to Generic long write command
Commits
- d61300 drm: xlnx: dsi: Add Generic long write command support

2020.1

no changes

2019.2

Summary
- Added support to DCS command mode
Commits
- 5f0013 drm: xlnx: dsi: Add command mode support

2019.1

Summary
- Added support for clock framework
- Updated the drm property creation logic
Commits
- 9d61db1 drm: xlnx: dsi: Fix the drm property creation
- 3792d72 drm: xlnx: dsi: Add support for clock framework
- 26a8a4d Merge tag 'v4.19' into master

2018.3

Summary
- Disabling bridge when DSI is disabled
- Fix a kernel panic when "halt" is run
Commits
- 3a1266e drm: xlnx: dsi: Fix kernel panic when "halt" is run
- b3314af drm: xlnx: dsi: Disable bridge instance

2018.2

Summary
- No change

2018.1

Summary
- Added xlnx bridge support
- Initial version based on new xlnx drm framework
  - Driver now moved to different drivers/gpu/drm/xlnx/xlns_dsi.c
  - Older driver drivers/gpu/drm/xilinx/xilinx_drm_dsi.c not supported.
Commits
- a1a9719 drm: xlnx: dsi: Adding xlnx bridge support
- 4d08c57 drm: xlnx: dsi: Adding dsi driver to new framework

2017.4

Summary
- No changes

2017.3

Summary
- Fix the Horizontal Active calculation
- Other minor fixes
Commits
- 3a49cee drm: xilinx: dsi: Fixes the Hact calculation
- 00bf902 drm: xilinx: dsi: Fix for checkpatch
- 33ab072 drm: xilinx: dsi: Don't check unsigned with negative
- 434275c drm: xilinx: dsi: Add static and remove unused variable
- 9db27d0 drm: xilinx: dsi: Add const for constant callback functions
- 9c6f82c drm: xilinx: dsi: Change the documentation style

2017.2

Summary
- No changes

2017.1

Summary
- Initial version of driver added
Commits
- 63b99c0 drm: xilinx: mipi: DRM/KMS driver for MIPI DSI2 Tx subsystem

Xilinx DRM KMS MIPI DSI2-Tx Driver

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