TPG

v_tpg@a00e0000 {
compatible = "xlnx,v-tpg-8.2" , "xlnx,v-tpg-8.0";
xlnx,max-width = <3840>;
reset-gpios = <&gpio 96 1>;
xlnx,max-height = <2160>;
xlnx,vtc = <&tpg_input_v_tc_1>;
reg = <0x0 0xa00e0000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <8>;
xlnx,ppc = <2>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
tpg_portstpg_input_v_tpg_1: ports {
#address-cells = <1>;
#size-cells = <0>;
tpg_port1tpg_input_v_tpg_1: port@1 {
xlnx,video-width = <8>;
reg = <1>;
xlnx,video-format = <2>;
tpg_outtpg_input_v_tpg_1: endpoint {
remote-endpoint = <&tpg_input_v_frmbuf_wr_0>;
};
};
tpg_port0tpg_input_v_tpg_1: port@0 {
xlnx,video-width = <8>;
reg = <0>;
xlnx,video-format = <2>;
};
};
};

tpg_input_v_tc_1: v_tc@a00d0000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_4>, <&zynqmp_clk 71>;
compatible = "xlnx,v-tc-6.2", "xlnx,v-tc-6.1", "xlnx,bridge-v-tc-6.1";
reg = <0x0 0xa00d0000 0x0 0x10000>;
xlnx,generator ;
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

VPSS Scalar

v_proc_ss@a0080000 {
reset-gpios = <&psng0_axi_gpio_rst 3 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0080000 0x0 0x40000>;
xlnx,num-hori-taps = <6>;
xlnx,h-scaler-taps = <6>;
xlnx,topology = <0>;
compatible = "xlnx,v-proc-ss-2.3" , "xlnx,v-vpss-scaler-2.2";
xlnx,csc-enable-window = "true";
xlnx,max-width = <3840>;
xlnx,use-uram = <0>;
xlnx,v-scaler-taps = <6>;
xlnx,video-width = <8>;
xlnx,colorspace-support = <0>;
xlnx,num-vert-taps = <6>;
xlnx,pix-per-clk = <2>;
xlnx,enable-csc = "true";
xlnx,scaler-algorithm = <2>;
xlnx,v-scaler-phases = <64>;
clocks = <&misc_clk_2>, <&misc_clk_2>;
clock-names = "aclk_axis" , "aclk_ctrl";
xlnx,h-scaler-phases = <64>;
xlnx,samples-per-clk = <2>;
scaler_portspsng0_vpss_scaler: ports {
#address-cells = <1>;
#size-cells = <0>;
scaler_port1psng0_vpss_scaler: port@1 {
xlnx,video-width = <8>;
reg = <1>;
xlnx,video-format = <3>;
sca_outpsng0_vpss_scaler: endpoint {
remote-endpoint = <&psng0_v_frmbuf_wr_0psng0_vpss_scaler>;
};
};
scaler_port0psng0_vpss_scaler: port@0 {
xlnx,video-width = <8>;
reg = <0>;
xlnx,video-format = <3>;
psng0_vpss_scalerpsng0_vpss_csc: endpoint {
remote-endpoint = <&csc_outpsng0_vpss_csc>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

VPSS CSC

v_proc_ss@a0000000 {
reset-gpios = <&psng0_axi_gpio_rst 2 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0000000 0x0 0x10000>;
xlnx,h-scaler-taps = <6>;
xlnx,topology = <3>;
xlnx,csc-enable-window = "false";
compatible = "xlnx,v-proc-ss-2.3" , "xlnx,v-vpss-csc";
xlnx,max-width = <3840>;
xlnx,use-uram = <0>;
xlnx,v-scaler-taps = <6>;
xlnx,video-width = <8>;
xlnx,colorspace-support = <0>;
xlnx,scaler-algorithm = <2>;
xlnx,v-scaler-phases = <64>;
clocks = <&misc_clk_2>;
clock-names = "aclk";
xlnx,h-scaler-phases = <64>;
csc_portspsng0_vpss_csc: ports {
#address-cells = <1>;
#size-cells = <0>;
csc_port1psng0_vpss_csc: port@1 {
xlnx,video-width = <8>;
reg = <1>;
xlnx,video-format = <3>;
csc_outpsng0_vpss_csc: endpoint {
remote-endpoint = <&psng0_vpss_scalerpsng0_vpss_csc>;
};
};
csc_port0psng0_vpss_csc: port@0 {
xlnx,video-width = <8>;
reg = <0>;
xlnx,video-format = <3>;
psng0_vpss_cscpsng0_vg0: endpoint {
remote-endpoint = <&gamma_outpsng0_vg0>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Demosaic

v_demosaic@a0010000 {
compatible = "xlnx,v-demosaic-1.1" , "xlnx,v-demosaic";
xlnx,max-width = <3840>;
reset-gpios = <&psng0_axi_gpio_rst 0 1>;
xlnx,max-height = <2160>;
xlnx,use-uram = <0>;
reg = <0x0 0xa0010000 0x0 0x10000>;
clocks = <&misc_clk_2>;
xlnx,s-axi-ctrl-addr-width = <6>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
demosaic_portspsng0_dm0: ports {
#address-cells = <1>;
#size-cells = <0>;
demosaic_port1psng0_dm0: port@1 {
reg = <1>;
demo_outpsng0_dm0: endpoint {
remote-endpoint = <&psng0_vg0psng0_dm0>;
};
};
demosaic_port0psng0_dm0: port@0 {
reg = <0>;
psng0_dm0csirx_0: endpoint {
remote-endpoint = <&mipi_csirx_outcsirx_0>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Gamma Lut

v_gamma_lut@a0020000 {
compatible = "xlnx,v-gamma-lut-1.1" , "xlnx,v-gamma-lut";
xlnx,max-width = <3840>;
reset-gpios = <&psng0_axi_gpio_rst 1 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0020000 0x0 0x10000>;
clocks = <&misc_clk_2>;
xlnx,s-axi-ctrl-addr-width = <13>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
gamma_portspsng0_vg0: ports {
#address-cells = <1>;
#size-cells = <0>;
gamma_port1psng0_vg0: port@1 {
xlnx,video-width = <8>;
reg = <1>;
gamma_outpsng0_vg0: endpoint {
remote-endpoint = <&psng0_vpss_cscpsng0_vg0>;
};
};
gamma_port0psng0_vg0: port@0 {
xlnx,video-width = <8>;
reg = <0>;
psng0_vg0psng0_dm0: endpoint {
remote-endpoint = <&demo_outpsng0_dm0>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Mixer

hdmi_output_v_mix_0: v_mix@a0070000 {
reset-gpios = <&gpio 98 1>;
reg = <0x0 0xa0070000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <13>;
xlnx,ppc = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-mix-5.2" , "xlnx,mixer-3.0" , "xlnx,mixer-4.0" , "xlnx,mixer-5.0";
xlnx,num-layers = <9>;
xlnx,video-format = <0>;
interrupt-parent = <&imux>;
xlnx,bpc = <8>;
interrupts = < 0 95 4 >;
clocks = <&misc_clk_0>;
xlnx,dma-addr-width = <64>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
xlnx,max-rows = <2160>;
xlnx,max-data-width = <8>;
crtc_mixer_porthdmi_output_v_mix_0: port@0 {
reg = <0>;
mixer_crtchdmi_output_v_mix_0: endpoint {
remote-endpoint = <&hdmi_output_v_hdmi_tx_ss_0hdmi_output_v_mix_0>;
};
};
xx_mix_masterhdmi_output_v_mix_0: layer_0 {
xlnx,layer-primary;
xlnx,layer-max-height = <2160>;
xlnx,vformat = "BG24";
dmas = <&hdmi_output_v_frmbuf_rd_0 0>;
xlnx,layer-id = <0>;
xlnx,layer-streaming;
dma-names = "dma0";
xlnx,layer-max-width = <3840>;
};
xx_mix_overlay_1hdmi_output_v_mix_0: layer_1 {
xlnx,vformat = "NV12";
xlnx,layer-id = <1>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_2hdmi_output_v_mix_0: layer_2 {
xlnx,vformat = "NV12";
xlnx,layer-id = <2>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_3hdmi_output_v_mix_0: layer_3 {
xlnx,vformat = "NV12";
xlnx,layer-id = <3>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_4hdmi_output_v_mix_0: layer_4 {
xlnx,vformat = "NV12";
xlnx,layer-id = <4>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_5hdmi_output_v_mix_0: layer_5 {
xlnx,vformat = "NV12";
xlnx,layer-id = <5>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_6hdmi_output_v_mix_0: layer_6 {
xlnx,vformat = "NV12";
xlnx,layer-id = <6>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_7hdmi_output_v_mix_0: layer_7 {
xlnx,vformat = "NV12";
xlnx,layer-id = <7>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_8hdmi_output_v_mix_0: layer_8 {
xlnx,vformat = "NV12";
xlnx,layer-id = <8>;
xlnx,layer-max-width = <1920>;
};
xx_mix_logohdmi_output_v_mix_0: logo {
xlnx,logo-width = <64>;
xlnx,logo-height = <64>;
xlnx,layer-id = <9>;
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Frame Buffer Write

v_frmbuf_wr@a0070000 {
reset-gpios = <&psng0_axi_gpio_rst 4 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0070000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,pixels-per-clock = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-frmbuf-wr-2.5" , "xlnx,axi-frmbuf-wr-v2.2";
xlnx,max-width = <3840>;
xlnx,vid-formats = "rgb888" , "bgr888" , "xbgr8888" , "xrgb8888" , "uyvy" , "y8" , "vuy888" , "xvuy8888" , "yuyv" , "nv12" , "nv16";
interrupt-parent = <&imux>;
xlnx,video-width = <8>;
interrupts = < 0 107 4 >;
clocks = <&misc_clk_2>;
xlnx,dma-align = <16>;
xlnx,dma-addr-width = <32>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <0x20>;
#dma-cells = <1>;
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Frame Buffer Read

v_frmbuf_rd@a0040000 {
reset-gpios = <&psng0_axi_gpio_rst 5 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0060000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,pixels-per-clock = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-frmbuf-rd-2.5" , "xlnx,axi-frmbuf-rd-v2.2";
xlnx,max-width = <3840>;
xlnx,vid-formats = "bgr888";
interrupt-parent = <&imux>;
xlnx,video-width = <8>;
interrupts = < 0 106 4 >;
clocks = <&misc_clk_2>;
xlnx,dma-align = <16>;
xlnx,dma-addr-width = <32>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <0x20>;
#dma-cells = <1>;
}

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Multi-scalar

v_multi_scaler_0: v_multi_scaler@a0020000 {
reset-gpios = <&axi_gpio_0 0 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0020000 0x0 0x20000>;
xlnx,pixels-per-clock = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-multi-scaler-1.2" , "xlnx,v-multi-scaler-v1.0";
xlnx,max-width = <3840>;
xlnx,max-chan = <8>;
xlnx,num-taps = <6>;
xlnx,vid-formats = "rgb888" , "xrgb8888" , "bgr888" , "xbgr8888" , "xbgr2101010" , "uyvy" , "y8" , "y10" , "vuy888" , "xvuy8888" , "yuvx2101010" , "yuyv" , "nv12" , "nv16" , "xv20" , "xv15";
interrupt-parent = <&imux>;
interrupts = < 0 89 4 >;
clocks = <&zynqmp_clk 71>;
xlnx,dma-addr-width = <0x40>;
clock-names = "ap_clk";
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

HDMI Video PHY

vid_phy_controller: vid_phy_controller@80050000 {
xlnx,transceiver-width = <2>;
xlnx,rx-clk-primitive = <0>;
reg = <0x00 0x80050000 0x00 0x10000>;
interrupt-names = "irq";
compatible = "xlnx,vid-phy-controller-2.2" , "xlnx,vid-phy-controller-2.1";
xlnx,rx-max-gt-line-rate = <0x5aa320>;
xlnx,hdmi-fast-switch = <1>;
interrupt-parent = <&imux>;
xlnx,nidru-refclk-sel = <4>;
xlnx,tx-protocol = <1>;
xlnx,input-pixels-per-clock = <2>;
interrupts = < 0 89 4 >;
xlnx,tx-pll-selection = <6>;
clocks = <&zynqmp_clk 71>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_4>, <&misc_clk_4>, <&misc_clk_4>, <&misc_clk_4>, <&zynqmp_clk 71>, <&misc_clk_2>, <&zynqmp_clk 71>, <&misc_clk_2>;
clock-names = "drpclk" , "gtsouthrefclk0_in" , "gtsouthrefclk0_odiv2_in" , "mgtrefclk0_pad_n_in" , "mgtrefclk0_pad_p_in" , "mgtrefclk1_pad_n_in" , "mgtrefclk1_pad_p_in" , "vid_phy_axi4lite_aclk" , "vid_phy_rx_axi4s_aclk" , "vid_phy_sb_aclk" , "vid_phy_tx_axi4s_aclk";
xlnx,tx-buffer-bypass = <1>;
xlnx,nidru = <1>;
xlnx,rx-pll-selection = <0>;
xlnx,transceiver-type = <5>;
xlnx,tx-max-gt-line-rate = <0x5aa320>;
xlnx,rx-refclk-sel = <1>;
xlnx,use-gt-ch4-hdmi = <0>;
xlnx,tx-refclk-sel = <0>;
xlnx,rx-protocol = <1>;
xlnx,tx-clk-primitive = <0>;
xlnx,rx-no-of-channels = <3>;
xlnx,tx-no-of-channels = <3>;
vid_phy_controllerrxphy_lane0: vid_phy_rx_axi4s_ch0v_hdmi_rx_ss {
#phy-cells = <4>;
};
vid_phy_controllerrxphy_lane1: vid_phy_rx_axi4s_ch1v_hdmi_rx_ss {
#phy-cells = <4>;
};
vid_phy_controllerrxphy_lane2: vid_phy_rx_axi4s_ch2v_hdmi_rx_ss {
#phy-cells = <4>;
};
vid_phy_controllertxphy_lane0: vid_phy_tx_axi4s_ch0v_hdmi_tx_ss {
#phy-cells = <4>;
};
vid_phy_controllertxphy_lane1: vid_phy_tx_axi4s_ch1v_hdmi_tx_ss {
#phy-cells = <4>;
};
vid_phy_controllertxphy_lane2: vid_phy_tx_axi4s_ch2v_hdmi_tx_ss {
#phy-cells = <4>;
};
};

&zynq_us_ss_0_fmch_axi_iic {
/* Si5324 i2c clock generator /
si5324: clock-generator@68 {
compatible = "silabs,si5324";
reg = <0x68>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/ input clock(s); the XTAL is hard-wired on the ZCU102 board /
clocks = <&refhdmi>;
clock-names = "xtal";
/ output clocks /
clk0 {
reg = <0>;
/ HDMI TX reference clock output frequency */
clock-frequency = <27000000>;
};

};

/* DP159 exposes a virtual CCF clock. Upon .set_rate(), it adapts its retiming/driving behaviour */
dp159: hdmi-retimer@5e {
compatible = "ti,dp159";
reg = <0x5e>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
};
};

&v_hdmi_tx_ss {
clocks = <&misc_clk_1>, <&zynqmp_clk 71>, <&audio_ss_0_clk_wiz 0>, <&zynqmp_clk 72>, <&misc_clk_0>, <&si5324 0>, <&dp159>;
clock-names = "link_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk","txref-clk", "retimer-clk";
};

&vid_phy_controller{
clock-names = "drpclk" , "gtsouthrefclk0_in" , "gtsouthrefclk0_odiv2_in" , "mgtrefclk0_pad_n_in" , "mgtrefclk0_pad_p_in" , "mgtrefclk1_pad_n_in" , "mgtrefclk1_pad_p_in" , "vid_phy_axi4lite_aclk" , "vid_phy_rx_axi4s_aclk" , "vid_phy_sb_aclk" , "vid_phy_tx_axi4s_aclk", "dru-clk";
clocks = <&zynqmp_clk 71>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_3>, <&zynqmp_clk 71>, <&misc_clk_1>, <&zynqmp_clk 71>, <&misc_clk_1>, <&si570_2>;
};

HDMI RxSs v2.0

v_hdmi_rx_ss: v_hdmi_rx_ss@80000000 {
xlnx,audio-enabled;
interrupts = < 0 90 4 >;
compatible = "xlnx,v-hdmi-rx-ss-3.2" , "xlnx,v-hdmi-rx-ss-3.1";
interrupts = <0x00 0x5a 0x04>;
xlnx,edid-ram-size = <256>;
interrupt-parent = <&imux>;
reg = <0x0 0x80000000 0x0 0x10000>;
clocks = <&misc_clk_2>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&misc_clk_1>;
xlnx,vid-interface = <0>;
xlnx,max-bits-per-component = <8>;
xlnx,snd-pcm = <&audio_ss_audio_formatter_0>;
phy-names = "hdmi-phy0" , "hdmi-phy1" , "hdmi-phy2";
phys = <&vid_phy_controllerrxphy_lane0 0 1 1 0>, <&vid_phy_controllerrxphy_lane1 0 1 1 0>, <&vid_phy_controllerrxphy_lane2 0 1 1 0>;
clock-names = "link_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk";
xlnx,input-pixels-per-clock = <2>;
interrupt-names = "irq";
hdmirx_portsv_hdmi_rx_ss: ports {
#address-cells = <1>;
#size-cells = <0>;
hdmirx_portv_hdmi_rx_ss: port@0 {
reg = <0>;
xlnx,video-width = <10>;
xlnx,video-format = <0>;
hdmirx_outv_hdmi_rx_ss: endpoint {
remote-endpoint = <&v_frmbuf_wrv_hdmi_rx_ss>;
};
};
};
};

v_hdmi_tx_ss: v_hdmi_tx_ss@80020000 {
xlnx,audio-enabled;
interrupts = < 0 91 4 >;
compatible = "xlnx,v-hdmi-tx-ss-3.2" , "xlnx,v-hdmi-tx-ss-3.1";
xlnx,xlnx-hdmi-acr-ctrl = <&audio_ss_hdmi_acr_ctrl_0>;
interrupt-parent = <&imux>;
reg = <0x0 0x80020000 0x0 0x20000>;
clock-names = "link_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk";
clocks = <&misc_clk_2>, <&zynqmp_clk 71>, <&misc_clk_0>, <&zynqmp_clk 72>, <&misc_clk_1>;
xlnx,vid-interface = <0>;
xlnx,max-bits-per-component = <8>;
xlnx,snd-pcm = <&audio_ss_audio_formatter_0>;
phy-names = "hdmi-phy0" , "hdmi-phy1" , "hdmi-phy2";
phys = <&vid_phy_controllertxphy_lane0 0 1 1 1>, <&vid_phy_controllertxphy_lane1 0 1 1 1>, <&vid_phy_controllertxphy_lane2 0 1 1 1>;
xlnx,input-pixels-per-clock = <2>;
interrupt-names = "irq";
hdmitx_portsv_hdmi_tx_ss: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_hdmi_portv_hdmi_tx_ss: port@0 {
reg = <0>;
encoderv_hdmi_tx_ss: endpoint {
remote-endpoint = <&v_frmbuf_rdv_hdmi_tx_ss>;
};
};
};
};

HDMI 2.1 PHY

v_hdmi_phy1@80030000 {
xlnx, transceiver-width = <4>;
xlnx, rx-clk-primitive = <0x0>;
reg = <0x00 0x80030000 0x00 0x10000>;
interrupt-names = "irq";
compatible = "xlnx,v-hdmi-phy1-1.0";
xlnx, rx-max-gt-line-rate = <0xc>;
xlnx, hdmi-fast-switch = <1>;
interrupt-parent = <&imux>;
xlnx, nidru-refclk-sel = <4>;
xlnx, tx-protocol = <2>;
xlnx, input-pixels-per-clock = <4>;
interrupts = <0 89 4>;
xlnx, tx-pll-selection = <6>;
xlnx, rx-frl-refclk-sel = <0>;
clock-names = "drpclk", "gtnorthrefclk00_in", "gtnorthrefclk01_in", "gtnorthrefclk0_in", "gtnorthrefclk0_odiv2_in", "gtsouthrefclk0_in", "gtsouthrefclk0_odiv2_in", "mgtrefclk0_pad_n_in", "mgtrefclk0_pad_p_in", "vid_phy_axi4lite_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_tx_axi4s_aclk";
clocks = <&zynqmp_clk 71>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_4>, <&misc_clk_4>, <&misc_clk_3>, <&misc_clk_3>, <&zynqmp_clk 71>, <&misc_clk_0>, <&zynqmp_clk 71>, <&misc_clk_0>;
xlnx, tx-frl-refclk-sel = <2>;
xlnx, tx-buffer-bypass = <1>;
xlnx, nidru = <1>;
xlnx, rx-pll-selection = <0>;
xlnx, transceiver-type = <5>;
xlnx, tx-max-gt-line-rate = <0xc>;
xlnx, rx-refclk-sel = <0>;
xlnx, use-gt-ch4-hdmi = <1>;
xlnx, tx-refclk-sel = <2>;
xlnx, rx-protocol = <2>;
xlnx, tx-clk-primitive = <0>;
xlnx, rx-no-of-channels = <4>;
xlnx, tx-no-of-channels = <4>;
v_hdmi_phyrxphy_lane0: vid_phy_rx_axi4s_ch0v_hdmi_rxss1 {
#phy-cells = <4>;
};
v_hdmi_phyrxphy_lane1: vid_phy_rx_axi4s_ch1v_hdmi_rxss1 {
#phy-cells = <4>;
};
v_hdmi_phyrxphy_lane2: vid_phy_rx_axi4s_ch2v_hdmi_rxss1 {
#phy-cells = <4>;
};
v_hdmi_phyrxphy_lane3: vid_phy_rx_axi4s_ch3v_hdmi_rxss1 {
#phy-cells = <4>;
};
v_hdmi_phytxphy_lane0: vid_phy_tx_axi4s_ch0v_hdmi_txss1 {
#phy-cells = <4>;
};
v_hdmi_phytxphy_lane1: vid_phy_tx_axi4s_ch1v_hdmi_txss1 {
#phy-cells = <4>;
};
v_hdmi_phytxphy_lane2: vid_phy_tx_axi4s_ch2v_hdmi_txss1 {
#phy-cells = <4>;
};
v_hdmi_phytxphy_lane3: vid_phy_tx_axi4s_ch3v_hdmi_txss1 {
#phy-cells = <4>;
};

};

&amba_pl {
xfmc: xv_fmc {
compatible = "vfmc";
};

};
&amba {
ref40: ref40m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
};
&v_hdmi_txss1{
xlnx,max-frl-rate = <0x6>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2", "hdmi-phy3";
phys = <&v_hdmi_phytxphy_lane0 0 1 1 1>, <&v_hdmi_phytxphy_lane1 0 1 1 1>, <&v_hdmi_phytxphy_lane2 0 1 1 1>, <&v_hdmi_phytxphy_lane3 0 1 1 1>;
};
&v_hdmi_phy {
clock-names = "vid_phy_axi4lite_aclk", "drpclk", "tmds_clock", "frl_clock";
clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&idt_241 1>, <&si5344 1>;
xlnx,hdmi-connector = <&xfmc>;
rxch4-sel-gpios = <&vfmc_ctlr_ss_0_vfmc_gpio 18 0 1>;
};
&i2c1 {
si5344: clock-generator@68 {
compatible = "si5344";
#clock-cells = <1>;
reg = <0x68>;
clocks = <&ref40>;
clock-names = "xtal";
};
onsemi_tx: onsemi-tx@5b {
compatible = "onsemi,onsemi-tx";
#clock-cells = <1>;
reg = <0x5b>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};
onsemi_rx: onsemi-tx@5c {
compatible = "onsemi,onsemi-rx";
#clock-cells = <1>;
reg = <0x5c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};
idt_241: clock-generator@7c {
compatible = "idt,idt8t49";
#clock-cells = <1>;
reg = <0x7c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};
expander@75 {
compatible = "expander-fmc";
reg = <0x75>;
};
expander@74 {
compatible = "expander-fmc74";
reg = <0x74>;
};
expander@64 {
compatible = "expander-fmc64";
reg = <0x64>;
};
expander@65 {
compatible = "expander-fmc65";
reg = <0x65>;
};
expander@51 {
compatible = "expander-tipower";
reg = <0x51>;
};
};

&amba_pl {

ref40: ref40m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};

xfmc: xv_fmc {
compatible = "vfmc";
};
};
&cips_ss_0_axi_iic_0 {
idt_241: clock-generator@6c {
compatible = "idt,idt8t49";
#clock-cells = <1>;
reg = <0x6c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};

ti_tmds1204_tx: ti_tmds1204-tx@5e {
compatible = "ti_tmds1204,ti_tmds1204-tx";
#clock-cells = <1>;
reg = <0x5e>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};

ti_tmds1204_rx: ti_tmds1204-rx@5b {
compatible = "ti_tmds1204,ti_tmds1204-rx";
#clock-cells = <1>;
reg = <0x5b>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};

};
&hdmiphy_ss_0_hdmi_gt_controller {
clock-names = "vid_phy_axi4lite_aclk", "drpclk", "tmds_clock";
clocks = <&versal_clk 65>, <&versal_clk 65>, <&idt_241 1>;
xlnx,hdmi-connector = <&xfmc>;
};
&v_hdmi_txss1{
clock-names = "frl_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk", "link_clk";
clocks = <&misc_clk_4>, <&versal_clk 65>, <&audio_ss_0_clk_wizard 0>, <&misc_clk_3>, <&misc_clk_2>, <&misc_clk_2>;

};
&i2c0 {
expander@74 {
compatible = "expander-fmc74";
reg = <0x74>;
};
};

HDMI RxSs v2.1

v_hdmi_rxss1@80040000 {
interrupts = < 0 90 4 >;
compatible = "xlnx,v-hdmi-rxss1-1.2" , "xlnx,v-hdmi-rx-ss-3.1";
xlnx,edid-ram-size = /bits/ 16 <0x100>;
interrupt-parent = <&imux>;
xlnx,vid-clk-freq-khz = <0x61a80>;
xlnx,frl-clk-freq-khz = <0x6ddd0>;
reg = <0x00 0x80040000 0x00 0x10000>;
clocks = <&misc_clk_5>, <&misc_clk_0>, <&zynqmp_clk 71>, <&audio_ss_0_clk_wiz 0>, <&misc_clk_2>, <&misc_clk_4>;
xlnx,vid-interface = <0>;
xlnx,max-bits-per-component = /bits/ 8 <0xa>;
phys = <&v_hdmi_phyrxphy_lane0 0 1 1 0>, <&v_hdmi_phyrxphy_lane1 0 1 1 0>, <&v_hdmi_phyrxphy_lane2 0 1 1 0>, <&v_hdmi_phyrxphy_lane3 0 1 1 0>;
phy-names = "hdmi-phy0" , "hdmi-phy1" , "hdmi-phy2" , "hdmi-phy3";
clock-names = "frl_clk" , "link_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk";
xlnx,input-pixels-per-clock = /bits/ 8 <0x8>;
interrupt-names = "irq";
xlnx,max-frl-rate = /bits/ 8 <0x6>;
hdmirx_portsv_hdmi_rxss1: ports {
#address-cells = <1>;
#size-cells = <0>;
hdmirx_portv_hdmi_rxss1: port@0 {
reg = <0>;
xlnx,video-width = <10>;
xlnx,video-format = <0>;
hdmirx_outv_hdmi_rxss1: endpoint {
remote-endpoint = <&v_fb_ss_0_v_frmbuf_wr_0v_hdmi_rxss1>;
};
};
};
};

HDMI TxSs v2.1

v_hdmi_txss1@80060000 {
reg = <0x00 0x80060000 0x00 0x20000>;
xlnx,frl-clk-freq-khz = <0x6ddd0>;
phys = <&v_hdmi_phytxphy_lane0 0 1 1 1>, <&v_hdmi_phytxphy_lane1 0 1 1 1>, <&v_hdmi_phytxphy_lane2 0 1 1 1>, <&v_hdmi_phytxphy_lane2 0 1 1 1>;
interrupt-names = "irq";
compatible = "xlnx,v-hdmi-txss1-1.2";
interrupt-parent = <&imux>;
xlnx,xlnx-hdmi-acr-ctrl = <&audio_ss_0_hdmi_acr_ctrl>;
xlnx,vid-clk-freq-khz = <0x61a80>;
xlnx,max-bits-per-component = <10>;
xlnx,vid-interface = <0>;
phy-names = "hdmi-phy0" , "hdmi-phy1" , "hdmi-phy2" , "hdmi-phy3";
xlnx,input-pixels-per-clock = <8>;
xlnx,max-frl-rate = <6>;
interrupts = < 0 91 4 >;
clocks = <&misc_clk_5>, <&misc_clk_0>, <&zynqmp_clk 71>, <&audio_ss_0_clk_wiz 0>, <&misc_clk_2>, <&misc_clk_4>;
clock-names = "frl_clk" , "link_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk";
hdmitx_portsv_hdmi_txss1: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_hdmi_portv_hdmi_txss1: port@0 {
reg = <0>;
encoderv_hdmi_txss1: endpoint {
remote-endpoint = <&v_fb_ss_0_v_frmbuf_rd_0v_hdmi_txss1>;
};
};
};

};

HDMI Rx v2.1 with HDCP (Assume both HDCP 1x and 2x enabled)

            v_hdmi_rxss1: v_hdmi_rxss1@80080000 {

                                    xlnx,fec-enable = <1>;

                                    xlnx,exdes-topology = <0>;

                                    xlnx,hdmi-version = <4>;

                                    xlnx,rable = <0>;

                                    hdcp14-connected = <&v_hdmi_rxss1_hdcp_1_4>;

                                    xlnx,ip-name = "v_hdmi_rxss1";

                                    xlnx,frl-sm-vcke = <1>;

                                    reg = <0x0 0x80080000 0x0 0x80000>;

                                    xlnx,frl-clk-freq-khz = <0x6ddd0>;

                                    xlnx,vrr-support = <1>;

                                    phys = <&v_hdmi_phyrxphy_lane0 0 1 1 0>, <&v_hdmi_phyrxphy_lane1 0 1 1 0>, <&v_hdmi_phyrxphy_lane2 0 1 1 0>, <&v_hdmi_phyrxphy_lane3 0 1 1 0>;

                                    xlnx,include-hdcp-2-2;

                                    xlnx,include-hdcp;

                                    interrupt-names = "hdcp14_irq" , "hdcp14_timer_irq" , "hdcp22_irq" , "hdcp22_timer_irq" , "irq";

                                    xlnx,exdes-axilite-freq = <100>;

                                    xlnx,dsc-en = <0>;

                                    compatible = "xlnx,v-hdmi-rxss1-1.2" , "xlnx,v-hdmi-rx-ss-3.1";

                                    hdcp14-present = <1>;

                                    interrupt-parent = <&imux>;

                                    xlnx,num-of-gt-lane = <4>;

                                    xlnx,vid-clk-freq-khz = <0x61a80>;

                                    xlnx,exdes-nidru;

                                    xlnx,max-bits-per-component = /bits/ 8 <0x8>;

                                    xlnx,vid-interface = <0>;

                                    xlnx,exdes-tx-pll-selection = <6>;

                                    hdcp22-present = <1>;

                                    phy-names = "hdmi-phy0" , "hdmi-phy1" , "hdmi-phy2" , "hdmi-phy3";

                                    xlnx,cd-invert;

                                    status = "okay";

                                    xlnx,axi-lite-freq-hz = <0x5f5b9f5>;

                                    xlnx,input-pixels-per-clock = /bits/ 8 <0x8>;

                                    xlnx,include-yuv420-sup;

                                    xlnx,max-frl-rate = /bits/ 8 <0x6>;

                                    xlnx,name = "v_hdmi_rxss1";

                                    xlnx,include-low-reso-vid;

                                    interrupts = < 0 104 4 0 105 4 0 108 4 0 109 4 0 90 4 >;

                                    xlnx,dynamic-hdr = <0>;

                                    xlnx,addr-width = <10>;

                                    xlnx,exdes-rx-pll-selection = <0>;

                                    clocks = <&misc_clk_5>, <&misc_clk_0>, <&zynqmp_clk 71>, <&audio_ss_0_clk_wiz 0>, <&misc_clk_3>, <&misc_clk_4>;

                                    xlnx,edk-iptype = "PERIPHERAL";

                                    clock-names = "frl_clk" , "link_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk";

                                    hdcptimer-connected = <&v_hdmi_rxss1_axi_timer>;

                                    xlnx,highaddr = <0x800fffff>;

                                    xlnx,edid-ram-size = /bits/ 16 <0x100>;

                                    hdmirx1-present = <1>;

                                    hdmirx1-connected = <&v_hdmi_rxss1_v_hdmi_rx>;

                                    xlnx,add-core-dbg = <0>;

                                    hdcp22-connected = <&v_hdmi_rxss1_hdcp22_rx_ss>;

                                    xlnx,include-hdcp-1-4;

                                    hdcptimer-present = <1>;

                                    xlnx,hpd-invert;

                                    hdmirx_portsv_hdmi_rxss1: ports {

                                                #address-cells = <1>;

                                                #size-cells = <0>;

                                                hdmirx_portv_hdmi_rxss1: port@0 {

                                                            reg = <0>;

                                                            xlnx,video-width = <10>;

                                                            xlnx,video-format = <0>;

                                                            hdmirx_outv_hdmi_rxss1: endpoint {

                                                                        remote-endpoint = <&v_fb_ss_0_v_frmbuf_wr_0v_hdmi_rxss1>;

                                                            };

                                                };

                                    };

                        };

&amba_pl {
xfmc: xv_fmc {
compatible = "vfmc";
};

};
&amba {
ref40: ref40m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
};

&i2c1 {
si5344: clock-generator@68 {
compatible = "si5344";
#clock-cells = <1>;
reg = <0x68>;
clocks = <&ref40>;
clock-names = "xtal";
};

onsemi_tx: onsemi-tx@5b {
compatible = "onsemi,onsemi-tx";
#clock-cells = <1>;
reg = <0x5b>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};
onsemi_rx: onsemi-tx@5c {
compatible = "onsemi,onsemi-rx";
#clock-cells = <1>;
reg = <0x5c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};
idt_241: clock-generator@7c {
compatible = "idt,idt8t49";
#clock-cells = <1>;
reg = <0x7c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};

expander@75 {
compatible = "expander-fmc";
reg = <0x75>;
};
expander@74 {
compatible = "expander-fmc74";
reg = <0x74>;
};
expander@64 {
compatible = "expander-fmc64";
reg = <0x64>;
};
expander@65 {
compatible = "expander-fmc65";
reg = <0x65>;
};
expander@51 {
compatible = "expander-tipower";
reg = <0x51>;
};
};

&hdcp_keymngmt_blk_1 {
compatible = "xlnx,hdcp-keymngmt-blk-1.0", "syscon";
};

&hdcp_keymngmt_blk_0 {
compatible = "xlnx,hdcp-keymngmt-blk-1.0", "syscon";
};

&v_hdmi_txss1{
xlnx,max-frl-rate = <0x6>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2", "hdmi-phy3";
phys = <&v_hdmi_phytxphy_lane0 0 1 1 1>, <&v_hdmi_phytxphy_lane1 0 1 1 1>, <&v_hdmi_phytxphy_lane2 0 1 1 1>, <&v_hdmi_phytxphy_lane3 0 1 1 1>;
interrupt-names = "irq", "hdcp14", "hdcp14timer", "hdcp22", "hdcp22timer";
interrupts = <0 91 4 0 106 4 0 107 4 0 110 4 0 111 4 >;
};

HDCP 1x /2.2 RX keys need to be loaded.

HDMI Tx v2.1 with HDCP (Assume both HDCP 1x and 2x enabled)

            v_hdmi_txss1: v_hdmi_txss1@80100000 {

                                    xlnx,exdes-topology = <0>;

                                    xlnx,hdmi-version = <4>;

                                    xlnx,rable = <0>;

                                    hdcp14-connected = <&v_hdmi_txss1_hdcp_1_4>;

                                    xlnx,ip-name = "v_hdmi_txss1";

                                    xlnx,frl-sm-vcke = <0>;

                                    reg = <0x0 0x80100000 0x0 0x80000>;

                                    xlnx,frl-clk-freq-khz = <0x6ddd0>;

                                    xlnx,hysteresis-level = <511>;

                                    xlnx,vrr-support = <1>;

                                    vtc-present = <1>;

                                    phys = <&v_hdmi_phytxphy_lane0 0 1 1 1>, <&v_hdmi_phytxphy_lane1 0 1 1 1>, <&v_hdmi_phytxphy_lane2 0 1 1 1>, <&v_hdmi_phytxphy_lane3 0 1 1 1>;

                                    xlnx,include-hdcp-2-2;

                                    vtc-connected = <&v_hdmi_txss1_v_tc>;

                                    xlnx,include-hdcp;

                                    interrupt-names = "hdcp14_irq" , "hdcp14_timer_irq" , "hdcp22_irq" , "hdcp22_timer_irq" , "irq";

                                    xlnx,exdes-axilite-freq = <100>;

                                    xlnx,dsc-en = <0>;

                                    compatible = "xlnx,v-hdmi-txss1-1.2";

                                    xlnx,video-mask-enable = <1>;

                                    hdcp14-present = <1>;

                                    xlnx,native-exdes-en = <0>;

                                    xlnx,xlnx-hdmi-acr-ctrl = <&audio_ss_0_hdmi_acr_ctrl>;

                                    interrupt-parent = <&imux>;

                                    xlnx,num-of-gt-lane = <4>;

                                    xlnx,vid-clk-freq-khz = <0x61a80>;

                                    hdmitx1-present = <1>;

                                    xlnx,exdes-nidru;

                                    xlnx,max-bits-per-component = <8>;

                                    xlnx,vid-interface = <0>;

                                    xlnx,exdes-tx-pll-selection = <6>;

                                    hdcp22-present = <1>;

                                    phy-names = "hdmi-phy0" , "hdmi-phy1" , "hdmi-phy2" , "hdmi-phy3";

                                    status = "okay";

                                    xlnx,axi-lite-freq-hz = <0x5f5b9f5>;

                                    xlnx,input-pixels-per-clock = <8>;

                                    xlnx,include-yuv420-sup;

                                    xlnx,max-frl-rate = <6>;

                                    xlnx,name = "v_hdmi_txss1";

                                    xlnx,include-low-reso-vid;

                                    interrupts = < 0 106 4 0 107 4 0 110 4 0 111 4 0 91 4 >;

                                    xlnx,exdes-rx-pll-selection = <0>;

                                    xlnx,dynamic-hdr = <0>;

                                    xlnx,addr-width = <10>;

                                    clocks = <&misc_clk_5>, <&misc_clk_0>, <&zynqmp_clk 71>, <&audio_ss_0_clk_wiz 0>, <&misc_clk_3>, <&misc_clk_4>;

                                    xlnx,edk-iptype = "PERIPHERAL";

                                    clock-names = "frl_clk" , "link_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk";

                                    hdcptimer-connected = <&v_hdmi_txss1_axi_timer>;

                                    xlnx,highaddr = <0x8017ffff>;

                                    xlnx,hdcp-encrypt = <0x1>;

                                    xlnx,add-core-dbg = <0>;

                                    hdmitx1-connected = <&v_hdmi_txss1_v_hdmi_tx>;

                                    xlnx,hdcp-authenticate = <0x1>;

                                    hdcp22-connected = <&v_hdmi_txss1_hdcp22_tx_ss>;

                                    xlnx,include-hdcp-1-4;

                                    hdcptimer-present = <1>;

                                    xlnx,hpd-invert;

                                    hdmitx_portsv_hdmi_txss1: ports {

                                                #address-cells = <1>;

                                                #size-cells = <0>;

                                                encoder_hdmi_portv_hdmi_txss1: port@0 {

                                                            reg = <0>;

                                                            encoderv_hdmi_txss1: endpoint {

                                                                        remote-endpoint = <&v_fb_ss_0_v_frmbuf_rd_0v_hdmi_txss1>;

                                                            };

                                                };

                                    };

                        };

HDCP 2X keys need to be loaded.

SDI Tx

v_smpte_uhdsdi_tx_ss: v_smpte_uhdsdi_tx_ss@80020000 {
interrupts = < 0 90 4 0 108 4 >;
compatible = "xlnx,v-smpte-uhdsdi-tx-ss-2.0" , "xlnx,sdi-tx" , "xlnx,sdi-tx";
xlnx,include-edh;
xlnx,exdes-config = "Pass-through_with_Picxo";
xlnx,include-ycbcr-444 = <1>;
interrupt-parent = <&imux>;
xlnx,rable = <0>;
xlnx,ip-name = "v_smpte_uhdsdi_tx_ss";
reg = <0x0 0x80020000 0x0 0x20000>;
xlnx,sdiline-rate = <2>;
clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>;
xlnx,line-rate = "12G_SDI_8DS";
xlnx,tx-insert-c-str-st352 = "true";
xlnx,pixels-per-clock = <2>;
xlnx,bpp = <10>;
sditx-present = <1>;
xlnx,edk-iptype = "PERIPHERAL";
sdivtc-present = <1>;
xlnx,video-intf = "AXI4_Stream";
sditx-connected = <&v_smpte_uhdsdi_tx_ss_v_smpte_uhdsdi_tx>;
status = "okay";
xlnx,exdes-board = "ZCU106";
sdivtc-connected = <&v_smpte_uhdsdi_tx_ss_v_tc>;
clock-names = "s_axi_aclk" , "sdi_tx_clk" , "video_in_clk";
xlnx,Isstd_352 = <1>;
interrupt-names = "sdi_tx_irq" , "vtc_irq";
xlnx,include-adv-features;
xlnx,name = "v_smpte_uhdsdi_tx_ss";
xlnx,include-axilite;
xlnx,include-hfr = <1>;
sditx_portsv_smpte_uhdsdi_tx_ss: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_sdi_portv_smpte_uhdsdi_tx_ss: port@0 {
reg = <0>;
encoderv_smpte_uhdsdi_tx_ss: endpoint {
remote-endpoint = <&v_frmbuf_rd_0v_smpte_uhdsdi_tx_ss>;
};
};
sdi_audio_port: port@1 {
reg = <1>;
sdi_audio_sink_port: endpoint {
remote-endpoint = <&sditx_audio_embed_src>;
};
};
};
};

&amba_pl {
misc_clk_100: misc_clk_100 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
misc_clk_297: misc_clk_297 {
#clock-cells = <0>;
clock-frequency = <297000000>;
compatible = "fixed-clock";
};
misc_clk_300: misc_clk_300 {
#clock-cells = <0>;
clock-frequency = <300000000>;
compatible = "fixed-clock";
};
};
&si5328 {
compatible = "silabs,si5328";
reg =<0x69>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/*input clock(s); the xtal is hard-wired on the zcu106 board /
clock-names = "xtal";
/ output clocks */
clk0 {
reg = <0>;
/*QPLL1 reference clock output frequency */
clock-frequency = <148500000>;
};
};
&si570_2 {
clock-frequency = <148500000>;
};
&v_smpte_uhdsdi_tx_ss {
clock-names = "s_axi_aclk" , "sdi_tx_clk" , "video_in_clk";
clocks = <&misc_clk_100>, <&si5328 0>, <&misc_clk_297>;
phy-reset-gpio = <&axi_gpio_0 0 0 0>;
xlnx,qpll1_enabled = <0x1>;
};
&v_smpte_uhdsdi_rx_ss {
clock-names = "s_axi_aclk" , "sdi_rx_clk" , "video_out_clk";
clocks = <&misc_clk_100>, <&si570_2>, <&misc_clk_297>;
reset_gt-gpios = <&axi_gpio_1 0 0 0>;
};

Tx_Heir_v_smpte_uhdsdi_tx_ss_0: v_smpte_uhdsdi_tx_ss@a4040000 {
interrupts = < 0 85 4 >;
compatible = "xlnx,v-smpte-uhdsdi-tx-ss-2.0" , "xlnx,sdi-tx";
xlnx,include-edh;
xlnx,exdes-config = "Pass-through_with_Picxo";
xlnx,include-ycbcr-444 = <1>;
interrupt-parent = <&imux>;
xlnx,rable = <0>;
xlnx,ip-name = "v_smpte_uhdsdi_tx_ss";
reg = <0x0 0xa4040000 0x0 0x20000>;
xlnx,sdiline-rate = <2>;
clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>;
xlnx,line-rate = "12G_SDI_8DS";
xlnx,tx-insert-c-str-st352 = "true";
xlnx,pixels-per-clock = <2>;
xlnx,bpp = <10>;
sditx-present = <1>;
xlnx,edk-iptype = "PERIPHERAL";
sdivtc-present = <1>;
xlnx,video-intf = "AXI4_Stream";
sditx-connected = <&Tx_Heir_v_smpte_uhdsdi_tx_ss_0_v_smpte_uhdsdi_tx>;
xlnx,is-versal;
status = "okay";
xlnx,exdes-board = "ZCU106";
sdivtc-connected = <&Tx_Heir_v_smpte_uhdsdi_tx_ss_0_v_tc>;
clock-names = "s_axi_aclk" , "sdi_tx_clk" , "video_in_clk";
xlnx,Isstd_352 = <1>;
interrupt-names = "sdi_tx_irq";
xlnx,include-adv-features;
xlnx,name = "Tx_Heir_v_smpte_uhdsdi_tx_ss_0";
xlnx,include-axilite;
xlnx,include-hfr = <1>;
sditx_portsTx_Heir_v_smpte_uhdsdi_tx_ss_0: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_sdi_portTx_Heir_v_smpte_uhdsdi_tx_ss_0: port@0 {
reg = <0>;
encoderTx_Heir_v_smpte_uhdsdi_tx_ss_0: endpoint {
remote-endpoint = <&v_frmbuf_rd_0Tx_Heir_v_smpte_uhdsdi_tx_ss_0>;
};
};
sdi_audio_port: port@1 {
reg = <1>;
sdi_audio_sink_port: endpoint {
remote-endpoint = <&sditx_audio_embed_src>;
};
};
};
};

&amba_pl {
misc_clk_145: misc_clk_145 {
#clock-cells = <0>;
clock-frequency = <145000000>;
compatible = "fixed-clock";
};
misc_clk_297: misc_clk_297 {
#clock-cells = <0>;
clock-frequency = <297000000>;
compatible = "fixed-clock";
};
};
&Tx_Heir_v_smpte_uhdsdi_tx_ss_0 {
clocks = <&misc_clk_0>, <&misc_clk_145>, <&misc_clk_2>;
clock-names = "s_axi_aclk" , "sdi_tx_clk" , "video_in_clk";
};

SDI Rx

v_smpte_uhdsdi_rx_ss: v_smpte_uhdsdi_rx_ss@80000000 {
interrupts = < 0 89 4 >;
compatible = "xlnx,v-smpte-uhdsdi-rx-ss-2.0" , "xlnx,v-smpte-uhdsdi-rx-ss" , "xlnx,v-smpte-uhdsdi-rx-ss";
xlnx,include-edh;
xlnx,exdes-config = "Pass-Through";
xlnx,exdesboard-version = <2>;
xlnx,include-ycbcr-444;
interrupt-parent = <&imux>;
xlnx,rable = <0>;
xlnx,ip-name = "v_smpte_uhdsdi_rx_ss";
reg = <0x0 0x80000000 0x0 0x10000>;
xlnx,sdiline-rate = <2>;
clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>;
xlnx,line-rate = "12G_SDI_8DS";
sdirx-present = <1>;
xlnx,pixels-per-clock = <2>;
xlnx,bpp = <10>;
sdirx-connected = <&v_smpte_uhdsdi_rx_ss_v_smpte_uhdsdi_rx>;
xlnx,edk-iptype = "PERIPHERAL";
xlnx,video-intf = "AXI4_Stream";
status = "okay";
xlnx,exdes-board = "ZCU106";
clock-names = "s_axi_aclk" , "sdi_rx_clk" , "video_out_clk";
interrupt-names = "sdi_rx_irq";
xlnx,include-adv-features;
xlnx,include-hfr;
xlnx,name = "v_smpte_uhdsdi_rx_ss";
xlnx,include-axilite;
sdirx_portsv_smpte_uhdsdi_rx_ss: ports {
#address-cells = <1>;
#size-cells = <0>;
sdirx_portv_smpte_uhdsdi_rx_ss: port@0 {
reg = <0>;
xlnx,video-width = <10>;
xlnx,video-format = <0>;
sdirx_outv_smpte_uhdsdi_rx_ss: endpoint {
remote-endpoint = <&v_frmbuf_wr_0v_smpte_uhdsdi_rx_ss>;
};
};
};
};

&v_smpte_uhdsdi_rx_ss {
clock-names = "s_axi_aclk" , "sdi_rx_clk" , "video_out_clk";
clocks = <&misc_clk_100>, <&si570_2>, <&misc_clk_297>;
reset_gt-gpios = <&axi_gpio_1 0 0 0>;
};

RX_Heir_v_smpte_uhdsdi_rx_ss_0: v_smpte_uhdsdi_rx_ss@a4060000 {
interrupts = < 0 84 4 >;
compatible = "xlnx,v-smpte-uhdsdi-rx-ss-2.0" , "xlnx,v-smpte-uhdsdi-rx-ss";
xlnx,include-edh;
xlnx,exdes-config = "Pass-Through";
xlnx,exdesboard-version = <2>;
xlnx,include-ycbcr-444;
interrupt-parent = <&imux>;
xlnx,rable = <0>;
xlnx,ip-name = "v_smpte_uhdsdi_rx_ss";
reg = <0x0 0xa4060000 0x0 0x10000>;
xlnx,sdiline-rate = <2>;
clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>;
xlnx,line-rate = "12G_SDI_8DS";
sdirx-present = <1>;
xlnx,pixels-per-clock = <2>;
xlnx,bpp = <10>;
sdirx-connected = <&RX_Heir_v_smpte_uhdsdi_rx_ss_0_v_smpte_uhdsdi_rx>;
xlnx,edk-iptype = "PERIPHERAL";
xlnx,video-intf = "AXI4_Stream";
status = "okay";
xlnx,exdes-board = "ZCU106";
clock-names = "s_axi_aclk" , "sdi_rx_clk" , "video_out_clk";
interrupt-names = "sdi_rx_irq";
xlnx,include-adv-features;
xlnx,include-hfr;
xlnx,name = "RX_Heir_v_smpte_uhdsdi_rx_ss_0";
xlnx,include-axilite;
sdirx_portsRX_Heir_v_smpte_uhdsdi_rx_ss_0: ports {
#address-cells = <1>;
#size-cells = <0>;
sdirx_portRX_Heir_v_smpte_uhdsdi_rx_ss_0: port@0 {
reg = <0>;
xlnx,video-width = <10>;
xlnx,video-format = <0>;
sdirx_outRX_Heir_v_smpte_uhdsdi_rx_ss_0: endpoint {
remote-endpoint = <&v_frmbuf_wr_0RX_Heir_v_smpte_uhdsdi_rx_ss_0>;
};
};
};
};

&RX_Heir_v_smpte_uhdsdi_rx_ss_0 {
clocks = <&misc_clk_0>, <&misc_clk_297>, <&misc_clk_2>;
clock-names = "s_axi_aclk" , "sdi_rx_clk" , "video_out_clk";
};

DP Video PHY

                vid_phy_controller_0: vid_phy_controller@a0120000 {

                                    xlnx,tx-outclk-buffer = "none";

                                    xlnx,check-valid-protocol = <0>;

                                    xlnx,transceiver-width = <2>;

                                    xlnx,tx-refclk-fabric-buffer = "none";

                                    xlnx,txrefclk-rdy-invert = <0>;

                                    xlnx,tx-dp-protocol = <0>;

                                    xlnx,user-loss = <20>;

                                    xlnx,for-upgrade-speedgrade = <0xfffffffe>;

                                    xlnx,silicon-revision = <0>;

                                    xlnx,rable = <0>;

                                    xlnx,vid-phy-rx-axi4s-ch-tdata-width = <32>;

                                    xlnx,tx-tmds-clk-buffer = "bufg";

                                    xlnx,ip-name = "vid_phy_controller";

                                    xlnx,rx-clk-primitive = <0>;

                                    reg = <0x0 0xa0120000 0x0 0x10000>;

                                    xlnx,drpclk-freq = <0x2624a66>;

                                    xlnx,vid-phy-status-sb-rx-tdata-width = <16>;

                                    xlnx,hdio-rx = <0>;

                                    xlnx,supportlevel = <1>;

                                    xlnx,check-pll-selection = <0>;

                                    xlnx,sub-core-name = "dpss_zcu102_pt_vid_phy_controller_0_0_gtwrapper";

                                    xlnx,vid-phy-axi4lite-addr-width = <10>;

                                    interrupt-names = "irq";

                                    xlnx,rx-outclk-buffer = "none";

                                    xlnx,vid-phy-control-sb-tx-tdata-width = <1>;

                                    compatible = "xlnx,vid-phy-controller-2.2" , "xlnx,vid-phy-controller-2.1";

                                    xlnx,rx-max-gt-line-rate = <0x7b98a0>;

                                    xlnx,tx-sb-ports;

                                    xlnx,for-upgrade-architecture = "zynquplus";

                                    xlnx,hdmi-fast-switch = <1>;

                                    xlnx,rx-video-clk-buffer = "bufg";

                                    xlnx,channel-enable = "X1Y8 , X1Y9 , X1Y10 , X1Y11";

                                    interrupt-parent = <&imux>;

                                    xlnx,transceiver = "GTHE4";

                                    xlnx,nidru-refclk-sel = <0>;

                                    xlnx,rx-gt-line-rate = <0x18b820>;

                                    xlnx,vid-phy-tx-axi4s-ch-int-tdata-width = <40>;

                                    xlnx,dru-refclk-fabric-buffer = "none";

                                    xlnx,err-irq-en = <0>;

                                    xlnx,vid-phy-rx-axi4s-ch-tuser-width = <12>;

                                    xlnx,tx-protocol = <0>;

                                    xlnx,vid-phy-status-sb-tx-tdata-width = <8>;

                                    xlnx,hdio-tx = <0>;

                                    status = "okay";

                                    xlnx,input-pixels-per-clock = <4>;

                                    xlnx,axi4lite-enable;

                                    xlnx,axi-aclk-freq-mhz = <0x5f5b9f5>;

                                    xlnx,name = "vid_phy_controller_0";

                                    xlnx,dru-gain-g1-p = <16>;

                                    interrupts = < 0 90 4 >;

                                    xlnx,rx-tdata-width = <32>;

                                    xlnx,tx-pll-selection = <2>;

                                    xlnx,vid-phy-tx-axi4s-ch-tdata-width = <32>;

                                    xlnx,for-upgrade-maxoptvol = <0xd5de0>;

                                    xlnx,edk-iptype = "PERIPHERAL";

                                    xlnx,speedgrade = <0xfffffffe>;

                                    xlnx,for-upgrade-package = "ffvb1156";

                                    clock-names = "drpclk" , "gtnorthrefclk00_in" , "gtnorthrefclk01_in" , "gtnorthrefclk0_in" , "gtnorthrefclk10_in" , "gtnorthrefclk11_in" , "gtnorthrefclk1_in" , "gtsouthrefclk00_in" , "gtsouthrefclk01_in" , "gtsouthrefclk0_in" , "gtsouthrefclk10_in" , "gtsouthrefclk11_in" , "gtsouthrefclk1_in" , "mgtrefclk0_in" , "mgtrefclk1_in" , "vid_phy_axi4lite_aclk" , "vid_phy_rx_axi4s_aclk" , "vid_phy_sb_aclk" , "vid_phy_tx_axi4s_aclk";

                                    xlnx,int-hdmi-ver-cmptble = <3>;

                                    xlnx,int-width = <0>;

                                    xlnx,rx-sb-ports;

                                    xlnx,tx-gt-ref-clock-freq = <162>;

                                    xlnx,tx-buffer-bypass = <0>;

                                    xlnx,nidru = <0>;

                                    xlnx,rx-dp-protocol = <0>;

                                    xlnx,rx-pll-selection = <0>;

                                    xlnx,tx-tdata-width = <32>;

                                    xlnx,transceiver-type = <5>;

                                    xlnx,tx-max-gt-line-rate = <0x7b98a0>;

                                    xlnx,rx-tmds-clk-buffer = "bufg";

                                    xlnx,vid-phy-rx-axi4s-ch-int-tdata-width = <40>;

                                    xlnx,vid-phy-axi4lite-data-width = <32>;

                                    xlnx,tx-video-clk-buffer = "bufg";

                                    xlnx,for-upgrade-refvol = <0xcf850>;

                                    xlnx,rx-refclk-sel = <1>;

                                    xlnx,use-gt-ch4-hdmi = <0>;

                                    xlnx,for-upgrade-part = "xczu9eg-ffvb1156-2-e";

                                    xlnx,tx-refclk-sel = <0>;

                                    xlnx,tx-clk-primitive = <0>;

                                    xlnx,for-upgrade-device = "xczu9eg";

                                    xlnx,rx-protocol = <0>;

                                    xlnx,tx-gt-line-rate = <0x18b820>;

                                    xlnx,channel-site = "X1Y8";

                                    xlnx,adv-clk-mode;

                                    xlnx,dru-gain-g1 = <9>;

                                    xlnx,vid-phy-tx-axi4s-ch-tuser-width = <12>;

                                    xlnx,dru-gain-g2 = <4>;

                                    xlnx,rx-no-of-channels = <4>;

                                    xlnx,rx-gt-ref-clock-freq = <162>;

                                    xlnx,vid-phy-control-sb-rx-tdata-width = <8>;

                                    xlnx,device = "xczu9eg";

                                    xlnx,tx-no-of-channels = <4>;

                                    xlnx,component-name = "dpss_zcu102_pt_vid_phy_controller_0_0";

                                    vid_phy_controller_0rxphy_lane0: vid_phy_rx_axi4s_ch0dp_rx_hier_0_v_dp_rxss1_0 {

                                                #phy-cells = <4>;

                                    };

                                    vid_phy_controller_0rxphy_lane1: vid_phy_rx_axi4s_ch1dp_rx_hier_0_v_dp_rxss1_0 {

                                                #phy-cells = <4>;

                                    };

                                    vid_phy_controller_0rxphy_lane2: vid_phy_rx_axi4s_ch2dp_rx_hier_0_v_dp_rxss1_0 {

                                                #phy-cells = <4>;

                                    };

                                    vid_phy_controller_0rxphy_lane3: vid_phy_rx_axi4s_ch3dp_rx_hier_0_v_dp_rxss1_0 {

                                                #phy-cells = <4>;

                                    };

                                    vid_phy_controller_0txphy_lane0: vid_phy_tx_axi4s_ch0dp_tx_hier_0_v_dp_txss1_0 {

                                                #phy-cells = <4>;

                                    };

                                    vid_phy_controller_0txphy_lane1: vid_phy_tx_axi4s_ch1dp_tx_hier_0_v_dp_txss1_0 {

                                                #phy-cells = <4>;

                                    };

                                    vid_phy_controller_0txphy_lane2: vid_phy_tx_axi4s_ch2dp_tx_hier_0_v_dp_txss1_0 {

                                                #phy-cells = <4>;

                                    };

                                    vid_phy_controller_0txphy_lane3: vid_phy_tx_axi4s_ch3dp_tx_hier_0_v_dp_txss1_0 {

                                                #phy-cells = <4>;

                                    };

                        };

&vid_phy_controller_0 {
clock-names = "axi-lite", "drpclk";
clocks = <&zynqmp_clk 71>, <&zynqmp_clk 73>;
xlnx,xilinx-vfmc = &xfmcdp_tx_hier_0_v_dp_txss1_0;
};

DP v1.4 Rx without HDCP

dp_rx_hier_0_v_dp_rxss1_0: v_dp_rxss1@a0000000 {

                                    xlnx,include-clk-wiz = <0>;

                                    xlnx,num-streams = <1>;

                                    xlnx,pixel-mode = <4>;

                                    xlnx,inc-hdcp-keymngmt-blk = <0>;

                                    xlnx,include-axi-iic = <1>;

                                    xlnx,aux-io-loc = <1>;

                                    xlnx,rable = <0>;

                                    xlnx,ip-name = "v_dp_rxss1";

                                    reg = <0x0 0xa0000000 0x0 0x4000>;

                                    xlnx,include-clk-recov-support = <0>;

                                    xlnx,enable-420 = <0>;

                                    iic-present = <1>;

                                    phys = <&vid_phy_controller_0rxphy_lane0 0 1 1 0>, <&vid_phy_controller_0rxphy_lane1 0 1 1 0>, <&vid_phy_controller_0rxphy_lane2 0 1 1 0>,  <&vid_phy_controller_0rxphy_lane3 0 1 1 0>;

                                    iic-connected = <&dp_rx_hier_0_v_dp_rxss1_0_iic>;

                                    interrupt-names = "dprxss_dp_irq";

                                    xlnx,linkrate = <8100>;

                                    compatible = "xlnx,v-dp-rxss1-3.1" , "xlnx,v-dp-rxss-3.1"  , "xlnx,v-dp-rxss-3.0" ;

                                    xlnx,example-test-mode = "Disable";

                                    hdcp14-present = <0>;

                                    xlnx,max-resolution-for-420 = <0>;

                                    interrupt-parent = <&imux>;

                                    xlnx,support-artix-7series = <0>;

                                    hdcp22-present = <0>;

                                    xlnx,sim-mode = "Disable";

                                    phy-names = "dp-phy0" , "dp-phy1" , "dp-phy2" , "dp-phy3";

                                    xlnx,vidphy = <&vid_phy_controller_0>;

                                    xlnx,include-fec-ports = <0>;

                                    xlnx,bpc = <10>;

                                    xlnx,versal = <0>;

                                    xlnx,edp-enable = <0>;

                                    status = "okay";

                                    xlnx,clk-wiz-type = <2>;

                                    xlnx,phy-type-external = <1>;

                                    xlnx,axi-aclk-freq-mhz = <0x5f5b9f5>;

                                    dp14-present = <1>;

                                    xlnx,name = "dp_rx_hier_0_v_dp_rxss1_0";

                                    interrupts = < 0 89 4 >;

                                    dp14-connected = <&dp_rx_hier_0_v_dp_rxss1_0_dp>;

                                    xlnx,audio-channels = <2>;

                                    xlnx,mode = <0>;

                                    xlnx,video-interface = <0>;

                                    clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&misc_clk_1>, <&zynqmp_clk 72>, <&zynqmp_clk 71>;

                                    xlnx,egw-is-parent-ip = <0>;

                                    xlnx,enable-internal-remap = <1>;

                                    clkWiz-present = <0>;

                                    xlnx,edk-iptype = "PERIPHERAL";

                                    xlnx,start-dsc-byte-from-lsb = <1>;

                                    clock-names = "m_aud_axis_aclk" , "m_axis_aclk_stream1" , "rx_lnk_clk" , "rx_vid_clk" , "s_axi_aclk";

                                    xlnx,bits-per-color = <10>;

                                    xlnx,aux-io-type = <0>;

                                    xlnx,versal-board = <0>;

                                    xlnx,examplemodes = <1>;

                                    xlnx,phy-data-width = <2>;

                                    xlnx,enable-dsc = <0>;

                                    xlnx,enable-dsc-dummy-bytes-in-rx = <0>;

                                    xlnx,enable-8b10b-dec = <0>;

                                    xlnx,audio-enable = <1>;

                                    xlnx,lane-count = <4>;

                                    xlnx,int-debug = <0>;

                                    xlnx,link-rate = <30>;

                                    xlnx,include-vid-edid = <0>;

                                    hdcptimer-present = <0>;

                                    reg-names = "dp_base" , "edid_base";

                                    xlnx,dp-retimer = <&xfmcdp_rx_hier_0_v_dp_rxss1_0>;

                                    dprx_portsdp_rx_hier_0_v_dp_rxss1_0: ports {

                                                #address-cells = <1>;

                                                #size-cells = <0>;

                                                dprx_portdp_rx_hier_0_v_dp_rxss1_0: port@0 {

                                                            reg = <0>;

                                                };

                                                dprx_outdp_rx_hier_0_v_dp_rxss1_0: endpoint {

                                                            remote-endpoint = <&dp_rx_hier_0_v_frmbuf_wr_0dp_rx_hier_0_v_dp_rxss1_0>;

                                                };

                                    };

                        };

No changes

DP v1.4 Tx without HDCP

dp_tx_hier_0_v_dp_txss1_0: v_dp_txss1@a0010000 {

                                    xlnx,include-clk-wiz = <0>;

                                    xlnx,number-of-audio-channels = <2>;

                                    xlnx,num-streams = <1>;

                                    xlnx,pixel-mode = <4>;

                                    xlnx,aux-io-loc = <1>;

                                    xlnx,rable = <0>;

                                    xlnx,ip-name = "v_dp_txss1";

                                    reg = <0x0 0xa0010000 0x0 0x10000>;

                                    xlnx,enable-420 = <0>;

                                    phys = <&vid_phy_controller_0txphy_lane0 0 1 1 1>, <&vid_phy_controller_0txphy_lane1 0 1 1 1>, <&vid_phy_controller_0txphy_lane2 0 1 1 1>,  <&vid_phy_controller_0txphy_lane3 0 1 1 1>;

                                    xlnx,max-lanes = <4>;

                                    interrupt-names = "dptxss_dp_irq";

                                    xlnx,max-link-rate = <810000>;

                                    xlnx,linkrate = <8100>;

                                    compatible = "xlnx,v-dp-txss1-3.1" , "xlnx,v-dp-txss-3.1";

                                    xlnx,example-test-mode = "Disable";

                                    hdcp14-present = <0>;

                                    interrupt-parent = <&imux>;

                                    xlnx,num-audio-channels = <2>;

                                    xlnx,support-artix-7series = <0>;

                                    xlnx,ppc-for-420 = <4>;

                                    hdcp22-present = <0>;

                                    xlnx,sim-mode = "Disable";

                                    phy-names = "dp-phy0" , "dp-phy1" , "dp-phy2" , "dp-phy3";

                                    xlnx,enable-8b10b-enc = <0>;

                                    xlnx,include-fec-ports = <0>;

                                    xlnx,bpc = <10>;

                                    xlnx,versal = <0>;

                                    xlnx,edp-enable = <0>;

                                    status = "okay";

                                    xlnx,clk-wiz-type = <2>;

                                    xlnx,phy-type-external = <1>;

                                    xlnx,axi-aclk-freq-mhz = <0x5f5b9f5>;

                                    xlnx,vtc-offset = <0x8000>;

                                    dp14-present = <1>;

                                    xlnx,name = "dp_tx_hier_0_v_dp_txss1_0";

                                    interrupts = < 0 92 4 >;

                                    dual-splitter-present = <0>;

                                    dp14-connected = <&dp_tx_hier_0_v_dp_txss1_0_dp>;

                                    xlnx,mode = <0>;

                                    xlnx,video-interface = <0>;

                                    vtc1-present = <1>;

                                    xlnx,fec-encoder-delay = <16>;

                                    xlnx,egw-is-parent-ip = <0>;

                                    clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&zynqmp_clk 71>, <&misc_clk_1>, <&dp_tx_hier_0_clk_wiz_1 0>;

                                    xlnx,enable-internal-remap = <1>;

                                    xlnx,edk-iptype = "PERIPHERAL";

                                    xlnx,start-dsc-byte-from-lsb = <1>;

                                    clock-names = "s_axi_aclk" , "tx_vid_clk";

                                    xlnx,bits-per-color = <10>;

                                    xlnx,aux-io-type = <0>;

                                    xlnx,versal-board = <0>;

                                    xlnx,include-dual-splitter = <0>;

                                    xlnx,examplemodes = <0>;

                                    xlnx,phy-data-width = <2>;

                                    xlnx,enable-dsc = <0>;

                                    vtc1-connected = <&dp_tx_hier_0_v_dp_txss1_0_vtc1>;

                                    xlnx,audio-enable = <1>;

                                    xlnx,lane-count = <4>;

                                    xlnx,link-rate = <30>;

                                    xlnx,int-debug = <0>;

                                    hdcptimer-present = <0>;

                                    reg-names = "dp_base";

                                    xlnx,dp-retimer = <&xfmcdp_tx_hier_0_v_dp_txss1_0>;

                                    dptx_portsdp_tx_hier_0_v_dp_txss1_0: ports {

                                                #address-cells = <1>;

                                                #size-cells = <0>;

                                                dptx_portdp_tx_hier_0_v_dp_txss1_0: port@0 {

                                                            reg = <0>;

                                                            dptx_outdp_tx_hier_0_v_dp_txss1_0: endpoint {

                                                                        remote-endpoint = <&dp_tx_hier_0_v_frmbuf_rd_0dp_tx_hier_0_v_dp_txss1_0>;

                                                            };

                                                };

                                    };

                        };

&dp_rx_hier_0_v_frmbuf_wr_0 {
reset-gpios = <&dp_rx_hier_0_axi_gpio_1 0 1>;
};
&dp_tx_hier_0_v_frmbuf_rd_0 {
reset-gpios = <&dp_tx_hier_0_axi_gpio_0 0 1>;
};
&processor_hier_0_axi_iic_0 {
vfmc: vexpander@75 {
compatible = "expander-fmc";
reg = <0x75>;
};
expander@64 {
compatible = "expander-fmc64";
reg = <0x64>;
};
expander@65 {
compatible = "expander-fmc65";
reg = <0x65>;
};
expander@7c {
compatible = "expander-idt";
reg = <0x7c>;
};
expander@50 {
compatible = "expander-tipower";
reg = <0x51>;
};
expander@14 {
compatible = "expander-mcdp6000";
reg = <0x14>;
};
expander@05 {
compatible = "dp141";
reg = <0x05>;
};
};

&dp_tx_hier_0_v_dp_txss1_0 {
clock-names = "s_axi_aclk", "tx_vid_clk";
clocks = <&zynqmp_clk 71>, <&dp_tx_hier_0_clk_wiz_1 0>, <&misc_clk_1>, <&zynqmp_clk 71>;
};

DP v1.4 Tx with HDCP (Assume both HDCP 1x and 2x enabled)

MIPI CSI Rx

mipi_csi2_rx_subsystem@80000000 {
reg = <0x0 0x80000000 0x0 0x10000>;
xlnx,ppc = <2>;
xlnx,max-lanes = <4>;
interrupt-names = "csirxss_csi_irq";
compatible = "xlnx,mipi-csi2-rx-subsystem-6.0" , "xlnx,mipi-csi2-rx-subsystem-5.0";
xlnx,en-active-lanes;
xlnx,vfb;
interrupt-parent = <&imux>;
xlnx,en-vcx = <0>;
interrupts = < 0 92 4 >;
clocks = <&misc_clk_1>, <&misc_clk_0>, <&misc_clk_2>;
clock-names = "dphy_clk_200M" , "lite_aclk" , "video_aclk";
xlnx,csi-pxl-format = <0x2b>;
mipi_csi_portscsirx_0: ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_csi_port1csirx_0: port@1 {
xlnx,video-width = <8>;
reg = <1>;
xlnx,video-format = <12>;
xlnx,cfa-pattern = "rggb";
mipi_csirx_outcsirx_0: endpoint {
remote-endpoint = <&psng0_dm0csirx_0>;
};
};
mipi_csi_port0csirx_0: port@0 {
xlnx,video-width = <8>;
reg = <0>;
xlnx,video-format = <12>;
xlnx,cfa-pattern = "rggb";
mipi_csi_incsirx_0: endpoint {
data-lanes = < 1 2 3 4 >;
remote-endpoint = <&sensor_out>;
};
};
};
};

&axi_iic_1_sensor {
imx274: sensor@1a{
compatible = "sony,imx274";
reg = <0x1a>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 90 0>;
port@0 {
reg = <0>;
sensor_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&mipi_csi_incsirx_0>;
};
};
};
};

&mipi_csi_incsirx_0 {
remote-endpoint = <&sensor_out>;
};

TBD

TBD

NA

MIPI DSI Tx

mipi_dsi_tx_subsystem@80020000 {
reg = <0x0 0x80020000 0x0 0x20000>;
xlnx,dsi-data-type = <0>;
interrupt-names = "interrupt";
compatible = "xlnx,mipi-dsi-tx-subsystem-2.3" , "xlnx,dsi";
xlnx,dsi-num-lanes = <4>;
interrupt-parent = <&imux>;
interrupts = < 0 108 4 >;
clocks = <&misc_clk_1>, <&misc_clk_2>;
clock-names = "dphy_clk_200M" , "s_axis_aclk";
simple_paneldsi_display_path_dsitx_0: simple_panel@0 {
compatible = "auo,b101uan01";
reg = <0>;
};
encoder_dsi_portdsi_display_path_dsitx_0: port@0 {
reg = <0>;
encoderdsi_display_path_dsitx_0: endpoint {
remote-endpoint = <&dsi_display_path_v_frmbuf_rd_0dsi_display_path_dsitx_0>;
};
};
};

NA

TBD

TBD

Audio Formatter (MM2S/S2MM)

audio_formatter_0: audio_formatter@a4030000 {
xlnx,rx = <&RX_Heir_v_uhdsdi_audio_Extract>;
interrupts = < 0 90 4 0 91 4 >;
compatible = "xlnx,audio-formatter-1.0" , "xlnx,audio-formatter-1.0";
xlnx,packing-mode-mm2s = <0>;
xlnx,mm2s-async-clock = <1>;
xlnx,tx = <&Tx_Heir_v_uhdsdi_audio_Embed>;
xlnx,mm2s-addr-width = <64>;
interrupt-parent = <&imux>;
xlnx,rable = <0>;
xlnx,s2mm-dataformat = <1>;
xlnx,ip-name = "audio_formatter";
reg = <0x0 0xa4030000 0x0 0x10000>;
xlnx,include-s2mm = <1>;
xlnx,max-num-channels-mm2s = <2>;
clocks = <&misc_clk_3>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_2>;
xlnx,s2mm-async-clock = <1>;
xlnx,packing-mode-s2mm = <0>;
xlnx,edk-iptype = "PERIPHERAL";
xlnx,s2mm-addr-width = <64>;
status = "okay";
clock-names = "aud_mclk" , "m_axis_mm2s_aclk" , "s_axi_lite_aclk" , "s_axis_s2mm_aclk";
xlnx,mm2s-dataformat = <3>;
interrupt-names = "irq_mm2s" , "irq_s2mm";
xlnx,include-mm2s = <1>;
xlnx,max-num-channels-s2mm = <2>;
xlnx,name = "audio_formatter_0";
};

Note: Cross check the xlnx,tx and xlnx,rx properly pointed to respective Audio interface or not and aud_mclk clock value.

SDI Audio Embed

Tx_Heir_v_uhdsdi_audio_Embed: v_uhdsdi_audio@a4080000 {
interrupts = < 0 87 4 >;
compatible = "xlnx,v-uhdsdi-audio-2.0" , "xlnx,v-uhdsdi-audio-2.0";
xlnx,audio-function = <0>;
interrupt-parent = <&imux>;
xlnx,rable = <0>;
xlnx,sdi-aud-stat-ext;
xlnx,enable-clock-phase;
xlnx,ip-name = "v_uhdsdi_audio";
xlnx,aes-chan-stat-ext;
reg = <0x0 0xa4080000 0x0 0x10000>;
xlnx,axis-tid-width = <5>;
xlnx,sdiline-rate = <2>;
clocks = <&misc_clk_0>, <&misc_clk_2>, <&misc_clk_2>;
xlnx,enable-channel-padding;
xlnx,line-rate = "12G_SDI_8DS";
xlnx,snd-pcm = <&audio_formatter_0>;
xlnx,edk-iptype = "PERIPHERAL";
xlnx,num-audio-groups = <8>;
xlnx,max-audio-channels = <32>;
status = "okay";
clock-names = "s_axi_aclk" , "s_axis_clk" , "sdi_embed_clk";
interrupt-names = "interrupt";
xlnx,name = "Tx_Heir_v_uhdsdi_audio_Embed";
xlnx,include-axilite;
sdiTx_Heir_v_uhdsdi_audio_Embed: ports {
#address-cells = <1>;
#size-cells = <0>;
sdi_av_port: port@0 {
reg = <0>;
sditx_audio_embed_src: endpoint {
remote-endpoint = <&sdi_audio_sink_port>;
};
};
};
};

Note: In the audio pipeline creation make sure that xlnx,snd-pcm linking to correct audio formatter based on design.

SDI Audio Extract

RX_Heir_v_uhdsdi_audio_Extract: v_uhdsdi_audio@a4070000 {
interrupts = < 0 86 4 >;
compatible = "xlnx,v-uhdsdi-audio-2.0" , "xlnx,v-uhdsdi-audio-2.0";
xlnx,audio-function = <1>;
interrupt-parent = <&imux>;
xlnx,rable = <0>;
xlnx,sdi-aud-stat-ext;
xlnx,enable-clock-phase;
xlnx,ip-name = "v_uhdsdi_audio";
xlnx,aes-chan-stat-ext;
reg = <0x0 0xa4070000 0x0 0x10000>;
xlnx,axis-tid-width = <5>;
xlnx,sdiline-rate = <2>;
clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_2>;
xlnx,snd-pcm = <&audio_formatter_0>;
xlnx,enable-channel-padding;
xlnx,line-rate = "12G_SDI_8DS";
xlnx,sdi-rx-video = <&RX_Heir_v_smpte_uhdsdi_rx_ss_0>;
xlnx,edk-iptype = "PERIPHERAL";
xlnx,num-audio-groups = <8>;
xlnx,max-audio-channels = <32>;
status = "okay";
clock-names = "m_axis_clk" , "s_axi_aclk" , "sdi_extract_clk";
interrupt-names = "interrupt";
xlnx,name = "RX_Heir_v_uhdsdi_audio_Extract";
xlnx,include-axilite;
};

Note: In the audio pipeline creation make sure that xlnx,snd-pcm linking to correct audio formatter based on design.

HDMI GT PHY

hdmi_gt_controller@a4060000 {
xlnx,transceiver-width = <0x04>;
xlnx,rx-clk-primitive = <0x00>;
reg = <0x00 0xa4060000 0x00 0x10000>;
interrupt-names = "irq";
compatible = "xlnx,hdmi-gt-controller-1.0\0xlnx,v-hdmi-gt-controller-1.0";
xlnx,rx-max-gt-line-rate = <0x0c>;
xlnx,hdmi-fast-switch = <0x00>;
interrupt-parent = <0x4c>;
xlnx,nidru-refclk-sel = <0x02>;
xlnx,tx-protocol = <0x02>;
xlnx,input-pixels-per-clock = <0x04>;
interrupts = <0x00 0x54 0x04>;
xlnx,tx-pll-selection = <0x07>;
xlnx,rx-frl-refclk-sel = <0x02>;
clocks = <0x80 0x41 0x80 0x41 0xa5 0x01>;
xlnx,tx-frl-refclk-sel = <0x02>;
clock-names = "vid_phy_axi4lite_aclk\0drpclk\0tmds_clock";
xlnx,tx-buffer-bypass = <0x01>;
xlnx,nidru = <0x01>;
xlnx,rx-pll-selection = <0x08>;
xlnx,transceiver-type = <0x08>;
xlnx,tx-max-gt-line-rate = <0x0c>;
xlnx,rx-refclk-sel = <0x00>;
xlnx,use-gt-ch4-hdmi = <0x01>;
xlnx,tx-refclk-sel = <0x01>;
xlnx,gt-direction = <0x03>;
xlnx,rx-protocol = <0x02>;
xlnx,tx-clk-primitive = <0x00>;
xlnx,rx-no-of-channels = <0x04>;
xlnx,tx-no-of-channels = <0x04>;
xlnx,hdmi-connector = <0xa6>;
phandle = <0x12>;

};

&hdmiphy_ss_0_hdmi_gt_controller {
clock-names = "vid_phy_axi4lite_aclk", "drpclk", "tmds_clock";
clocks = <&versal_clk 65>, <&versal_clk 65>, <&idt_241 1>;
xlnx,hdmi-connector = <&xfmc>;
};

TBD

HDMI Rx v2.1 without HDCP

v_hdmi_rxss1@a4020000 {
interrupts = <0x00 0x55 0x04>;
compatible = "xlnx,v-hdmi-rxss1-1.2\0xlnx,v-hdmi-rx-ss-3.1";
xlnx,edid-ram-size = [01 00];
interrupt-parent = <0x4c>;
xlnx,vid-clk-freq-khz = <0x61a80>;
xlnx,frl-clk-freq-khz = <0x6ddd0>;
reg = <0x00 0xa4020000 0x00 0x10000>;
clocks = <0xa8 0x80 0x41 0x10 0x00 0xa7 0xa9>;
xlnx,vid-interface = <0x00>;
xlnx,max-bits-per-component = [08];
phy-names = "hdmi-phy0\0hdmi-phy1\0hdmi-phy2\0hdmi-phy3";
phys = <0xaa 0x00 0x01 0x01 0x00 0xab 0x00 0x01 0x01 0x00 0xac 0x00 0x01 0x01 0x00 0xad 0x00 0x01 0x01 0x00>;
clock-names = "frl_clk\0s_axi_cpu_aclk\0s_axis_audio_aclk\0s_axis_video_aclk\0video_clk";
xlnx,input-pixels-per-clock = [08];
interrupt-names = "irq";
xlnx,max-frl-rate = [06];
phandle = <0x0e>;

};

TBD

&amba_pl {

xfmc: xv_fmc {
compatible = "vfmc";
};
};
&cips_ss_0_axi_iic_0 {
idt_241: clock-generator@6c {
compatible = "idt,idt8t49";
#clock-cells = <1>;
reg = <0x6c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};

};
&i2c0 {
expander@74 {
compatible = "expander-fmc74";
reg = <0x74>;
};
};

HDMI Rx v2.1 with HDCP (Assume both HDCP 1x and 2x enabled)

TBD

HDMI RX HDCP Keys

HDMI Tx v2.1 without HDCP

v_hdmi_txss1@a4000000 {
reg = <0x00 0xa4000000 0x00 0x20000>;
xlnx,frl-clk-freq-khz = <0x6ddd0>;
phys = <0xaf 0x00 0x01 0x01 0x01 0xb0 0x00 0x01 0x01 0x01 0xb1 0x00 0x01 0x01 0x01 0xb1 0x00 0x01 0x01 0x01>;
interrupt-names = "irq";
compatible = "xlnx,v-hdmi-txss1-1.2";
interrupt-parent = <0x4c>;
xlnx,xlnx-hdmi-acr-ctrl = <0x11>;
xlnx,vid-clk-freq-khz = <0x61a80>;
xlnx,max-bits-per-component = <0x0a>;
xlnx,vid-interface = <0x00>;
phy-names = "hdmi-phy0\0hdmi-phy1\0hdmi-phy2\0hdmi-phy3";
xlnx,input-pixels-per-clock = <0x08>;
xlnx,max-frl-rate = <0x06>;
interrupts = <0x00 0x56 0x04>;
clocks = <0xa8 0x80 0x41 0x10 0x00 0xa7 0xa9 0xa9>;
clock-names = "frl_clk\0s_axi_cpu_aclk\0s_axis_audio_aclk\0s_axis_video_aclk\0video_clk\0link_clk";
phandle = <0x0d>;

};

&v_hdmi_txss1{
clock-names = "frl_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk", "link_clk";
clocks = <&misc_clk_4>, <&versal_clk 65>, <&audio_ss_0_clk_wizard 0>, <&misc_clk_3>, <&misc_clk_2>, <&misc_clk_2>;

};

TBD

&amba_pl {

xfmc: xv_fmc {
compatible = "vfmc";
};
};
&cips_ss_0_axi_iic_0 {
idt_241: clock-generator@6c {
compatible = "idt,idt8t49";
#clock-cells = <1>;
reg = <0x6c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};

};
&i2c0 {
expander@74 {
compatible = "expander-fmc74";
reg = <0x74>;
};
};

HDMI Tx v2.1 with HDCP (Assume both HDCP 1x and 2x enabled)

TBD

SDI Tx

NA

TBD

&sdi_rx_input_v_smpte_uhdsdi_rx_ss {
clock-names = "video_out_clk", "sdi_rx_clk", "s_axi_aclk";
clocks = <&zynqmp_clk 72>, <&si570_2>, <&zynqmp_clk 71>;
xlnx,picxo_enabled;
reset-gt-gpios = <&axi_gpio_0 0 0 1>;
picxo-reset-gpios = <&axi_gpio_0 2 0 0>;
};
&sdi_tx_output_v_smpte_uhdsdi_tx_ss {
clock-names = "sdi_tx_clk", "video_in_clk", "s_axi_aclk";
clocks = <&si570_2>, <&zynqmp_clk 72>, <&zynqmp_clk 71>;
xlnx,picxo_enabled;
};

&i2c1 {
i2c-mux@74 {
/delete-node/ i2c@2;
};
};

<Note: These custom changes vary based on input clocks. Here above example is for 2024.1 TRD design>

SDI Rx

NA

TBD

&sdi_rx_input_v_smpte_uhdsdi_rx_ss {
clock-names = "video_out_clk", "sdi_rx_clk", "s_axi_aclk";
clocks = <&zynqmp_clk 72>, <&si570_2>, <&zynqmp_clk 71>;
xlnx,picxo_enabled;
reset-gt-gpios = <&axi_gpio_0 0 0 1>;
picxo-reset-gpios = <&axi_gpio_0 2 0 0>;
};
&sdi_tx_output_v_smpte_uhdsdi_tx_ss {
clock-names = "sdi_tx_clk", "video_in_clk", "s_axi_aclk";
clocks = <&si570_2>, <&zynqmp_clk 72>, <&zynqmp_clk 71>;
xlnx,picxo_enabled;
};

&i2c1 {
i2c-mux@74 {
/delete-node/ i2c@2;
};
};

<Note: These custom changes vary based on input clocks. Here above example is for 2024.1 TRD design>

DP Video PHY

TBD

DP v1.4 Rx without HDCP

TBD

DP v1.4 Rx with HDCP (Assume both HDCP 1x and 2x enabled)

TBD

DP v1.4 Tx without HDCP

TBD

DP v1.4 Tx with HDCP (Assume both HDCP 1x and 2x enabled)

TBD

MIPI CSI Rx

TBD

MIPI DSI Tx

TBD

Audio Formatter (MM2S)

NA, refer above zynqMP audio formatter

TBD

NA

Note: In the audio pipeline creation make sure that xlnx,tx and xlnx,rx pointing to correct sound card or not based on design.

SPDIF Rx

NA, refer above zynqMP audio formatter

TBD

Note: In the audio pipeline creation make sure that xlnx,snd-pcm pointing to correct sound card or not based on design.