PL being the largest block on the SoC by area, it is a major power consumer too. This provides enormous opportunity to minimize power consumption in PL, thus reducing the overall power consumed. We will explore different build time and runtime techniques that can be employed to reduce PL power.
PL Static Power
PL doesn’t have power gating provisions like PS to control static power in unused parts of the logic. The only way to control static power is to control the voltage level. The option of using low power variants (-L) is attractive for users who have “low power” as a main design goal. Refer to “Device Selection” section for details.
Over that, there are some specific techniques which allow users to reduce the PL voltage and put it into retention state when there is no activity.
PL Dynamic Power
Controlling dynamic power in PL depends on the user logic, the application and activity profile involved. The default S/W stack provides some controls for PL power which if properly utilized in the user logic can yield power savings by being able to automatically enable Clock controls similar to PS peripherals. This technique leverages the PS->PL clocks that are provided in hardware and supported by PM framework. Custom PL IPs implemented by users can make use of runtime PM to enable the driver to push the IP into low power states when idle. This is achieved by implementing runtime PM handlers specific to that IP, which can suspend or resume the IP back on-demand.
Using PS->PL Clocks
There are four PS to PL clocks available to be used as clock sources for IPs in the PL. These clocks are similar to PS peripheral clocks and have controls like clock gating, dividers and PLL source section. They are modeled in PMUFW and can be controlled via EEMI clock control APIs.
Here is a screenshot of PS-PL clock controls in Vivado PCW Wizard:
These clocks can be controlled using clock management APIs in Linux similar to other PS clocks. PL IP drivers can configure these clocks as clock sources in device-tree and can manage these clocks at runtime. FCLK driver available in Xilinx Linux tree can be taken as reference for such drivers. Currently FCLK driver requests and holds these clock active.
Here is an example on exercising these clock APIs from Linux DebugFS interface:
# Get the current clock gate state
echo pm_clock_getstate 71 >/sys/kernel/debug/zynqmp-firmware/pm
# Disable/Gate the clock
echo pm_clock_disable 71 >/sys/kernel/debug/zynqmp-firmware/pm
# Enable/Ungate the clock
echo pm_clock_enable 71 >/sys/kernel/debug/zynqmp-firmware/pm
A more detailed explanation of clock control debugfs interface is provided in Linux PM wiki.
Using PMU GPOs to control power states
There are 32 PMU->PL General Purpose Outputs (GPOs) provided for general purpose usage. These are like EMIOs, but they can only be accessed and controlled by PMU. These GPOs can be re-purposed to be used as resets, clock-gates, sleep controls or power mode switches for PL IPs.
Here is a screen shot on enabling these GPOs in Vivado PCW wizard:
Here is a screen shot of a design which uses GPO as a sleep control signal for BRAM:
PMUFW provides EEMI reset control APIs to change the state of these GPOs. The node IDs for these GPOs are provided below:
Here is a debugfs example of these APIs which can control the PMU->PL GPOs:
# Control PMU->PL GPO- set to 1
echo pm_reset_assert 1081 1 >/sys/kernel/debug/zynqmp-firmware/pm
Clocking Wizard IP can be used to generate clocks for PL blocks. This IP supports dynamic reconfiguration using AXI interface, which enables us to change output clock frequency on the fly from Linux or any other App running on the PS processors. Design which can operate at different frequencies can use this feature to save power by switching to lower frequencies, depending on the use-case.
Here is a screen shot of enabling this feature in clocking wizard:
Additionally, there is a “Minimize Power” option which can be used to auto-select optimal configuration values to save power.