This page describes various techniques that can be applied to minimize and control programmable logic (PL) power in Zynq UltraScale+ MPSoC devices.

Introduction

PL being the largest block on the SoC by area, it is a major power consumer too. This provides enormous opportunity to minimize power consumption in PL, thus reducing the overall power consumed. We will explore different build time and runtime techniques that can be employed to reduce PL power.

PL Static Power

PL doesn’t have power gating provisions like PS to control static power in unused parts of the logic. The only way to control static power is to control the voltage level. The option of using low power variants (-L) is attractive for users who have “low power” as a main design goal. Refer to “Device Selection” section for details.

Over that, there are some specific techniques which allow users to reduce the PL voltage and put it into retention state when there is no activity.

PL Dynamic Power

Controlling dynamic power in PL depends on the user logic, the application and activity profile involved. The default S/W stack provides some controls for PL power which if properly utilized in the user logic can yield power savings by being able to automatically enable Clock controls similar to PS peripherals. This technique leverages the PS->PL clocks that are provided in hardware and supported by PM framework. Custom PL IPs implemented by users can make use of runtime PM to enable the driver to push the IP into low power states when idle. This is achieved by implementing runtime PM handlers specific to that IP, which can suspend or resume the IP back on-demand.

Using PS->PL Clocks

There are four PS to PL clocks available to be used as clock sources for IPs in the PL. These clocks are similar to PS peripheral clocks and have controls like clock gating, dividers and PLL source section. They are modeled in PMUFW and can be controlled via EEMI clock control APIs.

Here is a screenshot of PS-PL clock controls in Vivado PCW Wizard:

Here are the node IDs for these PS->PL clocks:

#define PM_CLOCK_PL0_REF                     71U

#define PM_CLOCK_PL1_REF                     72U

#define PM_CLOCK_PL2_REF                     73U

#define PM_CLOCK_PL3_REF                     74U

These clocks can be controlled using clock management APIs in Linux similar to other PS clocks. PL IP drivers can configure these clocks as clock sources in device-tree and can manage these clocks at runtime. FCLK driver available in Xilinx Linux tree can be taken as reference for such drivers. Currently FCLK driver requests and holds these clock active.

Here is an example on exercising these clock APIs from Linux DebugFS interface:

# Get the current clock gate state
echo pm_clock_getstate 71 >/sys/kernel/debug/zynqmp-firmware/pm

# Disable/Gate the clock
echo pm_clock_disable 71 >/sys/kernel/debug/zynqmp-firmware/pm

# Enable/Ungate the clock
echo pm_clock_enable 71 >/sys/kernel/debug/zynqmp-firmware/pm

A more detailed explanation of clock control debugfs interface is provided in Linux PM wiki.

Using PMU GPOs to control power states

There are 32 PMU->PL General Purpose Outputs (GPOs) provided for general purpose usage. These are like EMIOs, but they can only be accessed and controlled by PMU. These GPOs can be re-purposed to be used as resets, clock-gates, sleep controls or power mode switches for PL IPs.

Here is a screen shot on enabling these GPOs in Vivado PCW wizard:

Here is a screen shot of a design which uses GPO[0] as a sleep control signal for BRAM:

PMUFW provides EEMI reset control APIs to change the state of these GPOs. The node IDs for these GPOs are provided below:

PM_RESET_GPO3_PL_0	1081
PM_RESET_GPO3_PL_1	1082
PM_RESET_GPO3_PL_2	1083
PM_RESET_GPO3_PL_3	1084
PM_RESET_GPO3_PL_4	1085
PM_RESET_GPO3_PL_5	1086
PM_RESET_GPO3_PL_6	1087
PM_RESET_GPO3_PL_7	1088
PM_RESET_GPO3_PL_8	1089
PM_RESET_GPO3_PL_9	1090
PM_RESET_GPO3_PL_10	1091
PM_RESET_GPO3_PL_11	1092
PM_RESET_GPO3_PL_12	1093
PM_RESET_GPO3_PL_13	1094
PM_RESET_GPO3_PL_14	1095
PM_RESET_GPO3_PL_15	1096
PM_RESET_GPO3_PL_16	1097
PM_RESET_GPO3_PL_17	1098
PM_RESET_GPO3_PL_18	1099
PM_RESET_GPO3_PL_19	1100
PM_RESET_GPO3_PL_20	1101
PM_RESET_GPO3_PL_21	1102
PM_RESET_GPO3_PL_22	1103
PM_RESET_GPO3_PL_23	1104
PM_RESET_GPO3_PL_24	1105
PM_RESET_GPO3_PL_25	1106
PM_RESET_GPO3_PL_26	1107
PM_RESET_GPO3_PL_27	1108
PM_RESET_GPO3_PL_28	1109
PM_RESET_GPO3_PL_29	1110
PM_RESET_GPO3_PL_30	1111
PM_RESET_GPO3_PL_31	1112

Here is a debugfs example of these APIs which can control the PMU->PL GPOs:

# Control PMU->PL GPO[0]- set to 1
echo pm_reset_assert 1081 1 >/sys/kernel/debug/zynqmp-firmware/pm

Clocking Wizard

Clocking Wizard IP can be used to generate clocks for PL blocks. This IP supports dynamic reconfiguration using AXI interface, which enables us to change output clock frequency on the fly from Linux or any other App running on the PS processors. Design which can operate at different frequencies can use this feature to save power by switching to lower frequencies, depending on the use-case.

Here is a screen shot of enabling this feature in clocking wizard:

Additionally, there is a “Minimize Power” option which can be used to auto-select optimal configuration values to save power.

Clocking wizard has a Linux driver available, which makes changing the frequency at runtime easy. See the clocking wizard driver page for more information and usage of this driver.

Xilinx Wiki

Programmable Logic Power Management

Table of Contents

Introduction

PL Static Power

PL Dynamic Power

Using PS->PL Clocks

Using PMU GPOs to control power states

Clocking Wizard

Table of Contents

Introduction

PL Static Power

PL Dynamic Power

Using PS->PL Clocks

Using PMU GPOs to control power states

Clocking Wizard

Related Links