Introduction

This page provides information about the DesignWare I3C driver, which can be found on AMD/Xilinx Git and mainline as dw-i3c-master.c
The I3C controller supports the v1.0 standard and includes dynamic address assignment, data
transfer to legacy I2C destinations, broadcast, and CCC transfers. The controller can operate as
in the secondary configuration mode.

HW IP Features

• Hardware-assisted dynamic Address assignment support

• APB3 slave interface for register access

• Supports Data transfer to legacy I2C slaves

• Supports SDR mode up to 12MHZ

• Supports private transfers

• Supports slave mode polled transfer

• Supports broadcast and direct CCC transfers

• Supports Address assignment CCC transfer

• Supports threshold configuration for Tx, Rx and Response FIFOs

Known issues and limitations

• Transfers larger than FIFO are not supported with the current driver implementation.

Kernel Configuration

The following config options need to be enabled:
CONFIG_DW_I3C_MASTER

It depends on I3C and HAS_IOMEM

Open

Devicetree

Refer to Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml for complete description.

Example
The following example shows adding an I2C node to the devicetree on versal net:

Open

Test procedure

This section details the getting of values from the sensor interfaced to i3c:

Mainline Status

This driver is currently in sync with the mainline kernel driver.

ChangeLog

2024.2

None

2024.1

None

2023.2

None

2023.1

Summary

• Add a module parameter for scl timing

Commits

c0b1954 - i3c: master: dw: Add a module parameter for scl timing

2022.2

None

2022.1

Summary

• Drop redundant disec call

Commits

5c34b8e - i3c: master: dw: Drop redundant disec call

Related Links

Linux Drivers

linux-xlnx/drivers/i3c/master/dw-i3c-master.c at xilinx-v2024.1 · Xilinx/linux-xlnx