The purpose of this page is to describe the Linux V4L2 driver for the Xilinx HDMI 2.1 Receiver (RX) Subsystem Soft IP for Zynq UltraScale+ MPSoC and Versal Adaptive SoC.

Introduction

The HDMI 2.1 Receiver Subsystem is a feature-rich soft IP incorporating all of the necessary logic to properly interface with PHY layers and provide HDMI decoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI 2.1 RX-related IP sub-cores and outputs them as a single IP. The subsystem receives the captured TMDS/FRL data from the video PHY layer. It then extracts the video and audio streams from the HDMI stream and converts it to video and audio streams.
The HDMI 2.1 Receiver Subsystem is a MAC subsystem which works with a HDMIPHY/GT (PHY) controller to create a video connectivity system. The HDMI 2.1 Receiver Subsystem is tightly coupled with the Xilinx HDMIPHY/GT PHY Controller, which itself is independent and offer flexible architecture with multiple-protocol support. Both MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Figure 1. Block diagram of HDMI 2.1 Rx Subsystem

HDMIPHY Interface for Zynq UltraScale+ MPSoC

Figure 2. Block diagram of MAC interface

GT PHY Interface for Versal

Driver Overview

HDMI 2.1 RX is the first node in the capture pipeline. The Linux driver is implemented within the V4L2 framework and creates a subdev node which can be used to query and configure the hdmi-rx IP core. The RX driver provides an abstracted view of the feature set provided by each included sub-core. It dynamically manages the data and control flow through the processing elements, based on the input stream configuration detected at run time. Internally, it relies on sub-core drivers to configure the sub-core IP blocks.

AMD HDMI 2.1 RX Subsystem is tightly coupled with the AMD HDMIPHY/GT controller driver and manages the interaction with the PHY layer internally. The HDMIPHY/GT controller driver is an integral part of the solution and needs to be enabled along with the AMD HDMI 2.1 RX driver in the kernel configuration.

IP/Driver Features

IP Feature	2024.1

IP Feature	2024.1
HDMI 2.1 compatible	xlnx,v-hdmi-rx-ss-3.1
Dynamic support of FRL and TMDS	Yes
Dynamic support of FRL data rate (12 Gbps @ 4 lanes, 10 Gbps @ 4 lanes, 8 Gbps @ 4 lanes, 6 Gbps @ 4 lanes, 6 Gbps @ 3 lanes, and 3 Gbps @ 3 lanes)	Yes
Dynamic support of TMDS up to 6 Gbps @ 3 lanes	Yes
Supports both integer and non-integer frame rates	Yes
Supports FRL training patterns LTP5, LTP6, LTP7, LTP8, No LTP, and special symbols (0xFFE and 0xFFF).	Yes
Support of resolution up to 10,240 x 4,320 @ 30 fps (in FRL mode)	Tested up to 8k@60 (in FRL mode)
Support of 8k/10kp60 YUV420 (in FRL mode)	Tested up to 8k@60 YUV420(in FRL mode)
Support of 8, 10, 12, and 16 bits per component (BPC)	Tested 8, 10 bits per components.
Support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0 color formats	Yes
Support 4 and 8 pixels per clock (PPC) AXI4-Stream Video input	Yes
Supports 4 pixels per clock (PPC) Native Video and Native Video (Vectored DE) output stream	No
Supports L-PCM Audio up to 32 channels	No
High bit rate (HBR) Audio	No
3D audio support	No
Optional HDCP 2.3/1.4 decryption support	Supports HDCP 1.4
Info frames
Data Display Channel (DDC)	Yes
Cable Detect at active-High or Low polarity	Yes
Supports hot-plug detection at active-High or Low polarity	Yes
Supports HDR video transport (Dynamic Range and Mastering info frames) Traditional Gamma - SDR Traditional Gamma - HDR HDR 10 - SMPTE ST 2084 Hybrid Log Gamma (HLG)	No
Supports enhanced gaming and media features Variable Refresh Rate (VRR) Quick Frame Transport (QFT) Auto Low Latency Mode (ALLM) Quick Media Switching (QMS)	No
Supports VRR	No
Supports Dynamic HDR CTA 861-H HDR dynamic metadata extended info frame	No
Supports HDR10+ Forum VSIF	No
Supports Display Stream Compression (DSC) Pass Through	No

Kernel Configuration Options for Driver

2021.2 and later versions

Driver builds depending on CONFIG_VIDEO_XILINX_HDMI21RXSS configurable option. This option is present under “Device Drivers → Multimedia support → Media drivers ---> Media platform devices“as shown below.
Driver source can be found at linux-xlnx/drivers/media/platform/xilinx/xilinx-hdmirxss.c at master · Xilinx/linux-xlnx (github.com)

Device Tree Binding

The DTS node should be defined with correct hardware configuration. The method to define the node is documented in

2023.2: Documentation/devicetree/bindings/xlnx,v-hdmi-rxss1.yaml

2023.1: Documentation/devicetree/bindings/xlnx,v-hdmi-rxss1.yaml

2022.2: Documentation/devicetree/bindings/xlnx,v-hdmi-rxss1.yaml

2022.1: Documentation/devicetree/bindings/xlnx,v-hdmi-rxss1.yaml

2021.2: Documentation/devicetree/bindings/xlnx,v-hdmi-rxss1.yaml

Test procedure

HDMI 2.1 RX Subsystem IP is ready to accept data immediately after kernel boot-up. On cable connect, the RX core will detect the input stream and set the MEDIA_BUS format accordingly. A user can query the detected format by using the open-source media-ctl utility, available as part of the kernel.

A sample output of media-ctl for a 1080p60Hz input is shown below, where the capture pipeline has only an RX device node directly connected to a video node:

% media-ctl -p -d /dev/media0
 
 
Media controller API version 0.1.0
  
Media device information
------------------------
driver          xilinx-video
model           Xilinx Video Composite Device
serial
bus info
hw revision     0x0
driver version  0.0.0
  
Device topology
- entity 1: vcap_hdmi output 0 (1 pad, 1 link)
            type Node subtype V4L flags 0
            device node name /dev/video0
        pad0: Sink
                <- "a0000000.v_hdmi_rx_ss":0 [ENABLED]
  
- entity 5: a0000000.v_hdmi_rx_ss (1 pad, 1 link)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev0
        pad0: Source
                [fmt:RBG24/1920x1080 field:none]
                [dv.caps:BT.656/1120 min:0x0@25000000 max:4096x2160@297000000 stds:CEA-861,DMT,CVT,GTF caps:progressive,reduced-blanking,custom]
                [dv.detect:BT.656/1120 1920x1080p60 (2200x1125) stds:CEA-861 flags:CE-video]
                -> "vcap_hdmi output 0":0 [ENABLED]

To visualize the input frames, users can also use open-source utilities like YAVTA, to capture the frames to DDR and write them to SD card for offline viewing. This would require additional IP’s (for example, Xilinx Framebuffer Write) in the pipeline to write Rx data to DDR

Hdmi-Rx ==> FB_Wr (DMA) ==> DDR

For example, to capture a 1920x1080 stream, the following command is used:

yavta -n 3 -c10 -f YUYV -s 1920x1080 --skip 7 -F /dev/video0

The captured frames can then be processed by an application like raw2rgbpnm using a command similar to the following:

raw2rgbpnm -s1920x1080 -f YUYV 1920x1080.bin 1920x1080.pnm

The .pnm files are then viewed using a utility such as gimp

DEBUG Capability

The HDMI 2.1 RX Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to the serial console and can be viewed in the kernel dmesg buffer

Boards Supported

The Driver has been tested on the following boards.

ZCU102 Rev 1.1
VEK280 Rev B01

Xilinx Wiki

Xilinx V4L2 HDMI 2.1 RX Subsystem Driver

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