Introduction

The Xilinx® HDMI PHY Controller LogiCORE IP core is designed for enabling plug-and-play connectivity with Xilinx® HDMI™ 2.1 technology MAC transmit or receive subsystems. The interface between the video MAC and PHY layers are standardized to enable ease of use in accessing shared transceiver resources. The AXI4-Lite interface is provided to enable dynamic accesses of transceiver controls/status.

Figure 1: Video IP layer

Driver Overview

The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The HDMI PHY Controller IP/Driver is not intended to be used as a stand alone IP and must be used with Xilinx Video MACs such as the HDMI 2.1 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems. The core enables simpler connectivity between MAC layers for TX and RX paths.

As such PHY Linux Driver is implemented within the kernel PHY framework and is tightly coupled with HDMI 2.1 Rx/Tx Linux drivers. This driver also hosts the common video files shared between the 3 Xilinx connectivity drivers (HDMI PHY, HDMI 2.1 Rx and HDMI 2.1 Tx) and exports the relevant API’s for inter-driver communication. On kernel boot-up both HDMI 2.1 Rx & Tx drivers will request 4 PHY lanes each for Rx & Tx and will defer until PHY driver has been initialized.

IP/Driver Features

IP Feature	2022.1

IP Feature	2022.1
IP Version Supported	1.0
AXI4-Lite support for register accesses	Yes
Protocol Support: HDMI 2.1	Only HDMI 2.1
Full transceiver dynamic reconfiguration port (DRP) accesses and transceiver functions	Yes
Independent TX and RX path line rates (device specific)	Yes
Single quad support	Yes
Phase-locked loop (PLL) switching support from software	Yes
Transmit and Receiver user clocking	Yes
Protocol specific functions for HDMI (For example, HDMI Clock Detector)	Yes
Non-integer data recovery unit (NI-DRU) support for lower line rates. NI-DRU support is for the HDMI protocol only.	Yes
Use of 4th GT channel as TX TMDS clock	Yes
Advanced Clocking Support (Display Port protocol only)	Yes

HW IP Configuration

Kernel Configuration Options for Driver

CONFIG_PHY_XILINX_HDMIPHY should be enable enabled in the kernel configuration.

Device Tree Binding

The dts node should be defined with correct hardware configuration. How to define the node is documented in

2021.2: Documentation/devicetree/bindings/phy/xlnx,v-hmdi-phy1.yaml

2022.1: Documentation/devicetree/bindings/phy/xlnx,v-hmdi-phy1.yaml

DEBUG Capability

HDMI 2.1 PHY Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer.

How to capture register dump

Create a script on target and name it as dumpmem.sh. Paste below content in that script.

#!/bin/sh
# Usage dumpmem.sh ADDR OFFSET
base=$1
counter=0
while [ $counter -lt $2 ];
do
    offset=$(($counter*4))
    reg_addr=$(($base + $offset))
    reg_addr=`printf "0x%X\n" $reg_addr`
    output=$(devmem $reg_addr)
    delimiter=": "
    echo $reg_addr$delimiter$output
    counter=$(($counter+1))
done
echo All done

Now run below command to dump the registers of Vphy

# In the below command, first parameter is the base address of the IP (vphy) in this case and second parameter is the number of registers to be read
./dumpmem.sh 0x80120000 206

Boards Supported

Driver has been tested on following boards

zcu102 Rev 1.0

Change Log

2022.1

commits
- phy: xilinx-xhdmiphy: Set connector linerate in HDMI-RX TMDS mode
- phy: xilinx-xhdmiphy: Fix connector linerate setting in FRL mode

Xilinx Wiki

Xilinx HDMI 2.1 PHY driver

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