Xilinx DRM KMS HDMI 2.1 TX Subsystem Driver
- Gugulothu, Rajesh
- William Cassells (Unlicensed)
- Terry O'Neal (Unlicensed)
The purpose of this page is to describe the Linux DRM driver for the Xilinx HDMI 2.1 TX Subsystem Soft IP for Zynq UltraScale+ MPSoC and Versal Adaptive SoC.
Table of Contents
Introduction
The HDMI 2.1 Transmitter (TX) Subsystem is a feature-rich soft IP incorporating all of the necessary logic to properly interface with PHY layers and provide HDMI encoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI 2.1 TX-related IP sub-cores and outputs them as a single IP. It is an out-of-the-box ready-to-use HDMI 2.1 Transmitter Subsystem and avoids the need to manually assemble sub-cores to create a working HDMI system.
The subsystem takes incoming video and audio streams and transfers them to an HDMI stream. The stream is then forwarded to the video PHY layer.
The HDMI 2.1 Transmitter Subsystem is a MAC subsystem which works with a HDMI PHY Controller (HDMIPHY) to create a video connectivity system. The HDMI 2.1 Transmitter Subsystem is tightly coupled with the HDMIPHY Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.
HDMIPHY Interface for Zynq UltraScale+ MPSoC
The HDMI 2.1 TX Subsystem is a MAC subsystem which works with a HDMI PHY Controller (PHY) to create a video connectivity system. The HDMI 2.1 TX Subsystem is tightly coupled with the Xilinx Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.
GT PHY Interface for Versal
The HDMI 2.1 TX Subsystem is a MAC subsystem which works with a GT Controller (PHY) to create a video connectivity system. The HDMI 2.1 TX Subsystem is tightly coupled with the Xilinx GT Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.
Driver Overview
HDMI 2.1 TX is the last node in the display pipeline. The Linux driver is implemented as a sub-component of the Xilinx DRM KMS bridge driver and implements the encoder/connector interface. The subsystem includes the video timing generator and TX sub-core. Driver implements the DRM callbacks to read the display EDID and present it to the framework whenever a display is connected. It works in tandem with the DRM bridge driver to validate each mode listed in the EDID and reject unsupported modes.
On a mode change request from the user application, the driver works in conjunction with the DRM framework to validate the requested mode to ensure the stream can be generated by the TX core and is supported by the attached display. If the requested mode is supported, the driver will configure the TX sub-core for the new mode and the internal video timing controller (VTC) to generate the requisite video timing for it. It also configures the PHY layer for the new mode and manages all required interaction between the MAC and PHY layer.
Driver Features
IP Feature | 2024.1 | 2024.2 | 2025.1 |
|---|---|---|---|
compatible string | xlnx,v-hdmi-txss1-1.2 | xlnx,v-hdmi-txss1-1.2 | xlnx,v-hdmi-txss1-1.2 |
Dynamic support of TMDS and FRL modes | Yes | Yes | Yes |
Dynamic support of FRL data rate (12 Gb/s @ 4 lanes, 10 Gb/s @ 4 lanes, 8 Gb/s @ 4 lanes, 6Gb/s @ 4 lanes, 6 Gb/s @ 3 lanes, and 3 Gb/s @ 3 lanes) | Yes | Yes | Yes |
Dynamic support of TMDS up to 6 Gb/s 3 lanes | Yes | Yes | Yes |
Support resolutions up to 10,240 x 4,320 @ 30 fps (in FRL mode) | Tested up to 8k@60 YUV420 (in FRL mode) | Tested up to 8k@60 YUV420 (in FRL mode) | Tested up to 8k@60 YUV420 (in FRL mode) |
Support of 8k/10kp60 YUV420 (in FRL mode) | Tested up to 8k@60 YUV420 (in FRL mode) | Tested up to 8k@60 YUV420 (in FRL mode) | Tested up to 8k@60 YUV420 (in FRL mode) |
Support of 8, 10, 12, and 16 bits per component (BPC) | Tested 8, 10 bits per components. | Tested 8, 10 bits per components | Tested 8, 10, 12(yuv444 planar format) bits per components |
Support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0 color formats. | Yes | Yes | Yes |
Support 4 and 8 pixels per clock (PPC) AXI4-Stream Video input | Yes | Yes | Yes |
Supports 4 pixels per clock (PPC) Native Video and Native Video (Vectored DE) input stream. | No | No | No |
Supports L-PCM Audio up to 32 channels. | No | No | No |
High bit rate (HBR) Audio | No | No | No |
3D audio support | No | No | No |
Optional HDCP 2.3/1.4 encryption support | Yes | Yes | Yes |
Info frames | Yes | Yes | Yes |
Data Display Channel (DDC) | Yes | Yes | Yes |
Supports DDC clock stretching | Yes | Yes | Yes |
Supports hot-plug detection at active-High or Low polarity | Yes | Yes | Yes |
Supports HDR video transport (Dynamic Range and Mastering info frames) | No | No | No |
Supports enhanced gaming and media features | No | No | No |
Supports Dynamic HDR | No | No | No |
Supports HDR10+ Forum VSIF | No | No | No |
Kernel Configuration Options for Driver
2019.2 and later versions: Supports ONLY the new Xilinx DRM framework driver and PL crtc and can be enabled via the following configurations options: CONFIG_DRM_XLNX and CONFIG_DRM_XLNX_PL_DISP
The above defined options will only enable the new DRM framework.
Enable Xilinx HDMI 2.1 Transmitter Subsystem driver.
2021.2 and later versions: The HDMI 2.1 Tx driver is built as a part of the kernel, so enable the HDMI 2.1 Tx driver in the kernel configuration. Run the below command from the PetaLinux project and select "Xilinx DRM HDMI Subsystem Driver" present under “Device Drivers → Graohics support → Xilinx DRM KMS Driver” as shown below:
$petalinux-config -c kernel
Driver source can be found at linux-xlnx/drivers/gpu/drm/xlnx/xlnx_hdmi.c at master · Xilinx/linux-xlnx (github.com)
Device Tree Binding
The DTS node should be defined with correct hardware configuration. The method to define the node is documented in
2025.1: <update github link>
2024.2: Documentation/devicetree/bindings/display/xlnx/xlnx,v-hdmi-txss1.yaml
2024.1: Documentation/devicetree/bindings/display/xlnx/xlnx,v-hdmi-txss1.yaml
2023.2 : Documentation/devicetree/bindings/display/xlnx/xlnx,v-hdmi-txss1.yaml
2023.1 : Documentation/devicetree/bindings/display/xlnx/xlnx,v-hdmi-txss1.yaml
2022.2: Documentation/devicetree/bindings/display/xlnx/xlnx,v-hdmi-txss1.yaml
2022.1: Documentation/devicetree/bindings/display/xlnx/xlnx,v-hdmi-txss1.yaml
2021.2 : Documentation/devicetree/bindings/display/xlnx/xlnx,v-hdmi-txss1.yaml
Below is the example device tree for a design where the display pipeline flows from DDR memory through a framebuffer read DMA to an HDMI 2.1 transmitter. Below device tree nodes are generated by SDT.
v_hdmi_txss1: v_hdmi_txss1@a4000000 {
xlnx,exdes-topology = <0>;
xlnx,hdmi-version = <4>;
xlnx,rable = <0>;
xlnx,ip-name = "v_hdmi_txss1";
xlnx,frl-sm-vcke = <0>;
reg = <0x0 0xa4000000 0x0 0x20000>;
xlnx,frl-clk-freq-khz = <0x6ddd0>;
xlnx,hysteresis-level = <511>;
xlnx,vrr-support = <1>;
vtc-present = <1>;
phys = <&hdmiphy_ss_0_hdmi_gt_controllertxphy_lane0 0 1 1 1>, <&hdmiphy_ss_0_hdmi_gt_controllertxphy_lane1 0 1 1 1>, <&hdmiphy_ss_0_hdmi_gt_controllertxphy_lane2 0 1 1 1>, <&hdmiphy_ss_0_hdmi_gt_controllertxphy_lane2 0 1 1 1>;
vtc-connected = <&v_hdmi_txss1_v_tc>;
interrupt-names = "irq";
xlnx,exdes-axilite-freq = <100>;
xlnx,dsc-en = <0>;
compatible = "xlnx,v-hdmi-txss1-1.2";
xlnx,video-mask-enable = <1>;
hdcp14-present = <0>;
xlnx,native-exdes-en = <0>;
interrupt-parent = <&imux>;
xlnx,xlnx-hdmi-acr-ctrl = <&audio_ss_0_hdmi_acr_ctrl>;
xlnx,num-of-gt-lane = <4>;
xlnx,vid-clk-freq-khz = <0x61a80>;
hdmitx1-present = <1>;
xlnx,exdes-nidru;
xlnx,max-bits-per-component = <10>;
xlnx,vid-interface = <0>;
xlnx,exdes-tx-pll-selection = <7>;
hdcp22-present = <0>;
phy-names = "hdmi-phy0" , "hdmi-phy1" , "hdmi-phy2" , "hdmi-phy3";
status = "okay";
xlnx,axi-lite-freq-hz = <0x5f5e0a4>;
xlnx,input-pixels-per-clock = <8>;
xlnx,include-yuv420-sup;
xlnx,max-frl-rate = <6>;
xlnx,name = "v_hdmi_txss1";
xlnx,include-low-reso-vid;
interrupts = < 0 86 4 >;
xlnx,exdes-rx-pll-selection = <8>;
xlnx,dynamic-hdr = <0>;
xlnx,addr-width = <10>;
clocks = <&misc_clk_4>, <&versal_clk 65>, <&audio_ss_0_clk_wizard 0>, <&misc_clk_3>, <&misc_clk_2>;
xlnx,edk-iptype = "PERIPHERAL";
clock-names = "frl_clk" , "s_axi_cpu_aclk" , "s_axis_audio_aclk" , "s_axis_video_aclk" , "video_clk";
xlnx,highaddr = <0xa401ffff>;
xlnx,add-core-dbg = <0>;
hdmitx1-connected = <&v_hdmi_txss1_v_hdmi_tx>;
hdcptimer-present = <0>;
xlnx,hpd-invert;
hdmitx_portsv_hdmi_txss1: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_hdmi_portv_hdmi_txss1: port@0 {
reg = <0>;
encoderv_hdmi_txss1: endpoint {
remote-endpoint = <&v_fb_ss_0_v_frmbuf_rd_0v_hdmi_txss1>;
};
};
};
};
v_fb_ss_0_v_frmbuf_rd_0: v_frmbuf_rd@a4070000 {
xlnx,has-y-uv8 = <1>;
reset-gpios = <&v_fb_ss_0_axi_gpio 1 1>;
xlnx,max-height = <4320>;
xlnx,has-bgra8 = <0>;
xlnx,has-rgba8 = <0>;
xlnx,rable = <0>;
xlnx,ip-name = "v_frmbuf_rd";
reg = <0x0 0xa4070000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,pixels-per-clock = <8>;
xlnx,samples-per-clock = <8>;
xlnx,max-nr-planes = <3>;
xlnx,has-bgr8 = <1>;
xlnx,has-rgb8 = <1>;
xlnx,has-y-uv8-420 = <1>;
xlnx,has-yuyv8 = <1>;
xlnx,has-y-u-v8 = <1>;
interrupt-names = "interrupt";
compatible = "xlnx,v-frmbuf-rd-3.0" , "xlnx,axi-frmbuf-rd-v2.2";
xlnx,max-width = <8192>;
xlnx,has-rgb16 = <0>;
xlnx,vid-formats = "rgb888" , "xbgr8888" , "xrgb8888" , "bgr888" , "xbgr2101010" , "uyvy" , "y8" , "y10" , "vuy888" , "xvuy8888" , "yuvx2101010" , "yuyv" , "nv12" , "nv16" , "xv20" , "xv15" , "y_u_v8";
xlnx,has-bgrx8 = <1>;
xlnx,has-rgbx8 = <1>;
xlnx,has-rgbx10 = <1>;
interrupt-parent = <&imux>;
xlnx,aximm-num-outstanding = <4>;
xlnx,has-uyvy8 = <1>;
xlnx,has-rgbx12 = <0>;
xlnx,aximm-burst-length = <16>;
xlnx,aximm-addr-width = <32>;
xlnx,video-width = <10>;
xlnx,max-cols = <8192>;
xlnx,has-yuv8 = <1>;
status = "okay";
xlnx,has-y-uv10-420 = <1>;
xlnx,has-yuva8 = <0>;
xlnx,has-y-uv12-420 = <0>;
xlnx,name = "v_fb_ss_0_v_frmbuf_rd_0";
interrupts = < 0 91 4 >;
xlnx,fid;
xlnx,has-y10 = <1>;
xlnx,has-y-uv16-420 = <0>;
xlnx,has-y12 = <0>;
xlnx,has-alpha = <0>;
xlnx,has-y-u-v10 = <1>;
clocks = <&misc_clk_3>;
xlnx,has-y16 = <0>;
xlnx,dma-align = <64>;
xlnx,has-y-u-v12 = <0>;
xlnx,edk-iptype = "PERIPHERAL";
xlnx,has-interlaced = <1>;
xlnx,has-yuv16 = <0>;
xlnx,has-yuvx8 = <1>;
xlnx,is-tile-format = <0>;
xlnx,dma-addr-width = <32>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,has-y8 = <1>;
xlnx,has-y-uv10 = <1>;
xlnx,has-y-uv12 = <0>;
xlnx,max-rows = <4320>;
xlnx,has-yuvx10 = <1>;
#dma-cells = <1>;
xlnx,has-yuvx12 = <0>;
xlnx,has-y-uv16 = <0>;
xlnx,max-data-width = <10>;
xlnx,has-y-u-v8-420 = <1>;
xlnx,num-video-components = <3>;
xlnx,aximm-data-width = <512>;
};
v_pl_dispv_hdmi_txss1: drm-pl-disp-drvv_hdmi_txss1 {
compatible = "xlnx,pl-disp";
#address-cells = <1>;
xlnx,vformat = "YUYV";
dmas = <&v_fb_ss_0_v_frmbuf_rd_0 0>;
#size-cells = <0>;
dma-names = "dma0";
pl_display_portv_hdmi_txss1: port@0 {
reg = <0>;
v_fb_ss_0_v_frmbuf_rd_0v_hdmi_txss1: endpoint {
remote-endpoint = <&encoderv_hdmi_txss1>;
};
};
};
|
The following system-user.dtsi entries need to be appended for various platforms to support onboard redriver components, which cannot be generated by the SDT tool.
system-user.dtsi for VEK280/VEK385 platform
&amba_pl {
ref40: ref40m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
xfmc: xv_fmc {
compatible = "vfmc";
};
};
&cips_ss_0_axi_iic_0 {
idt_241: clock-generator@6c {
compatible = "idt,idt8t49";
#clock-cells = <1>;
reg = <0x6c>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};
ti_tmds1204_tx: ti_tmds1204-tx@5e {
compatible = "ti_tmds1204,ti_tmds1204-tx";
#clock-cells = <1>;
reg = <0x5e>;
clocks = <&ref40>;
clock-frequency = <148500000>;
clock-names = "input-xtal";
};
};
&hdmiphy_ss_0_hdmi_gt_controller {
clock-names = "vid_phy_axi4lite_aclk", "drpclk", "tmds_clock";
clocks = <&versal_clk 65>, <&versal_clk 65>, <&idt_241 1>;
xlnx,hdmi-connector = <&xfmc>;
};
system-user.dtsi for ZCU102/ZCU106 platform
&amba_pl { xfmc: xv_fmc { compatible = "vfmc"; }; }; &amba { ref40: ref40m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <40000000>; }; }; &v_hdmi_phy { clock-names = "vid_phy_axi4lite_aclk", "drpclk", "tmds_clock", "frl_clock"; clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&idt_241 1>, <&si5344 1>; xlnx,hdmi-connector = <&xfmc>; rxch4-sel-gpios = <&vfmc_ctlr_ss_0_vfmc_gpio 18 0 1>; }; &i2c1 { si5344: clock-generator@68 { compatible = "si5344"; #clock-cells = <1>; reg = <0x68>; clocks = <&ref40>; clock-names = "xtal"; }; onsemi_tx: onsemi-tx@5b { compatible = "onsemi,onsemi-tx"; #clock-cells = <1>; reg = <0x5b>; clocks = <&ref40>; clock-frequency = <148500000>; clock-names = "input-xtal"; }; idt_241: clock-generator@7c { compatible = "idt,idt8t49"; #clock-cells = <1>; reg = <0x7c>; clocks = <&ref40>; clock-frequency = <148500000>; clock-names = "input-xtal"; }; expander@75 { compatible = "expander-fmc"; reg = <0x75>; }; expander@74 { compatible = "expander-fmc74"; reg = <0x74>; }; expander@64 { compatible = "expander-fmc64"; reg = <0x64>; }; expander@65 { compatible = "expander-fmc65"; reg = <0x65>; }; expander@51 { compatible = "expander-tipower"; reg = <0x51>; }; };
Test procedure
Test procedure for video display
HDMI-Tx can be manually configured to generate the required mode. An open-source utility like modetest can be used to configure the display pipeline.
DDR ==> FB_Rd (DMA) ==> HDMI_2.1 Tx
2021.2 and later: The Sample command to set a mode is shown below:
%> modetest -D drm-pl-disp-drvv_hdmi_txss1 -s <connector_id>[@<crtc_id>]:<mode>[-<vrefresh>][@<format> |
Example command:
%> modetest -D drm-pl-disp-drvv_hdmi_txss1 -s 38:1920x1080-60@BG24 |
The above command will generate a color bar pattern at the requested resolution in DDR, configure the DMA to read the frame from DDR and configure the HDMI 2.1 TX for said resolution. As a final result, the Color Bar at the defined resolution should be visible on screen.
Expected output
<Update a color bar pic here>
The driver also supports changing output color formats dynamically. Available output color formats supported by DMA engine can be determined using the modetest utility as shown below:
root@xilinx-zcu102-2025_1:/media# modetest -D drm-pl-disp-drvv_hdmi_txss1
Encoders:
id crtc type possible crtcs possible clones
34 0 TMDS 0x00000001 0x00000000
Connectors:
id encoder status name size (mm) modes encoders
35 0 connected DP-1 700x390 39 34
modes:
name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
7680x4320 29.93 7680 7710 7720 7880 4320 4323 4328 4368 1030240 flags: phsync, nvsync; type: preferred, driver
7680x4320 24.00 7680 7728 7760 7880 4320 4323 4328 4369 826250 flags: phsync, nvsync; type: preferred, driver
3840x2160 60.00 3840 3888 3920 4000 2160 2163 2168 2222 533250 flags: phsync, nvsync; type: preferred, driver
3840x4320 60.00 3840 3888 3920 4040 4320 4323 4333 4368 1058790 flags: phsync, nvsync; type: driver
3840x4320 48.00 3840 3888 3920 4040 4320 4323 4333 4418 856720 flags: phsync, nvsync; type: driver
3840x2160 29.98 3840 3888 3920 4000 2160 2163 2168 2191 262750 flags: phsync, nvsync; type: driver
2560x1440 59.95 2560 2608 2640 2720 1440 1443 1448 1481 241500 flags: phsync, nvsync; type: driver
1920x1200 59.88 1920 2056 2256 2592 1200 1203 1209 1245 193250 flags: nhsync, pvsync; type: driver
2048x1080 59.99 2048 2096 2128 2208 1080 1083 1093 1111 147160 flags: phsync, nvsync; type: driver
2048x1080 23.90 2048 2096 2128 2208 1080 1083 1093 1099 58000 flags: phsync, nvsync; type: driver
1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: nhsync, nvsync; type: driver
1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
1920x1080 59.94 1920 2008 2052 2200 1080 1084 1089 1125 148352 flags: phsync, pvsync; type: driver
1920x1080 50.00 1920 2448 2492 2640 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
1920x1080 24.00 1920 2558 2602 2750 1080 1084 1089 1125 74250 flags: phsync, pvsync; type: driver
1920x1080 23.98 1920 2558 2602 2750 1080 1084 1089 1125 74176 flags: phsync, pvsync; type: driver
1600x1200 60.00 1600 1664 1856 2160 1200 1201 1204 1250 162000 flags: phsync, pvsync; type: driver
1680x1050 59.95 1680 1784 1960 2240 1050 1053 1059 1089 146250 flags: nhsync, pvsync; type: driver
1280x1024 75.02 1280 1296 1440 1688 1024 1025 1028 1066 135000 flags: phsync, pvsync; type: driver
1280x1024 60.02 1280 1328 1440 1688 1024 1025 1028 1066 108000 flags: phsync, pvsync; type: driver
1280x800 59.81 1280 1352 1480 1680 800 803 809 831 83500 flags: nhsync, pvsync; type: driver
1280x720 60.00 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: driver
1280x720 59.94 1280 1390 1430 1650 720 725 730 750 74176 flags: phsync, pvsync; type: driver
1280x720 50.00 1280 1720 1760 1980 720 725 730 750 74250 flags: phsync, pvsync; type: driver
1024x768 75.03 1024 1040 1136 1312 768 769 772 800 78750 flags: phsync, pvsync; type: driver
1024x768 60.00 1024 1048 1184 1344 768 771 777 806 65000 flags: nhsync, nvsync; type: driver
800x600 75.00 800 816 896 1056 600 601 604 625 49500 flags: phsync, pvsync; type: driver
800x600 60.32 800 840 968 1056 600 601 605 628 40000 flags: phsync, pvsync; type: driver
720x576 50.00 720 732 796 864 576 581 586 625 27000 flags: nhsync, nvsync; type: driver
720x576 50.00 720 732 796 864 576 581 586 625 27000 flags: nhsync, nvsync; type: driver
720x480 60.00 720 736 798 858 480 489 495 525 27027 flags: nhsync, nvsync; type: driver
720x480 60.00 720 736 798 858 480 489 495 525 27027 flags: nhsync, nvsync; type: driver
720x480 59.94 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type: driver
720x480 59.94 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type: driver
640x480 75.00 640 656 720 840 480 481 484 500 31500 flags: nhsync, nvsync; type: driver
640x480 60.00 640 656 752 800 480 490 492 525 25200 flags: nhsync, nvsync; type: driver
640x480 59.94 640 656 752 800 480 490 492 525 25175 flags: nhsync, nvsync; type: driver
640x480 59.94 640 656 752 800 480 490 492 525 25175 flags: nhsync, nvsync; type: driver
720x400 70.08 720 738 846 900 400 412 414 449 28320 flags: nhsync, pvsync; type: driver
props:
1 EDID:
flags: immutable blob
blobs:
value:
00ffffffffffff0010ac47414c353730
201b0104b54627783a7645ae5133ba26
0d5054a54b008100b300d100a9408180
d1c0010101014dd000a0f0703e803020
3500ba892100001a000000ff0046464e
584d3738373037354c0a000000fc0044
454c4c205550333231384b0a000000fd
00184b1eb46c010a2020202020200270
02031df150101f200514041312110302
161507060123091f0783010000a36600
a0f0701f8030203500ba892100001a56
5e00a0a0a0295030203500ba89210000
1a7c3900a080381f4030203a00ba8921
00001aa81600a08038134030203a00ba
892100001a0000000000000000000000
00000000000000000000000000000047
701279000012001682100000ff0edf10
000000000044454c47414c3537300301
5070920184ff1dc7001d800900df102f
0002000400c1420184ff1dc7002f801f
00df10300002000400a84e0104ff0ec7
002f801f00df10610002000900979d01
04ff0ec7002f801f00df102f00020009
00000000000000000000000000009890
2 DPMS:
flags: enum
enums: On=0 Standby=1 Suspend=2 Off=3
value: 3
5 link-status:
flags: enum
enums: Good=0 Bad=1
value: 0
6 non-desktop:
flags: immutable range
values: 0 1
value: 0
4 TILE:
flags: immutable blob
blobs:
value:
313a313a323a313a303a303a33383430
3a3433323000
21 CRTC_ID:
flags: object
value: 0
36 sync:
flags: range
values: 0 1
value: 0
37 bpc:
flags: enum
enums: 6BPC=6 8BPC=8 10BPC=10 12BPC=12
value: 8
CRTCs:
id fb pos size
33 0 (0,0) (0x0)
nan 0 0 0 0 0 0 0 0 0 flags: ; type:
props:
23 ACTIVE:
flags: range
values: 0 1
value: 0
24 MODE_ID:
flags: blob
blobs:
value:
20 OUT_FENCE_PTR:
flags: range
values: 0 18446744073709551615
value: 0
25 VRR_ENABLED:
flags: range
values: 0 1
value: 0
Planes:
id crtc fb CRTC x,y x,y gamma size possible crtcs
32 0 0 0,0 0,0 0 0x00000001
formats: XB30 VU24 XV30 YUYV XV20 BG24
props:
9 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 1
18 FB_ID:
flags: object
value: 0
19 IN_FENCE_FD:
flags: signed range
values: -1 2147483647
value: -1
21 CRTC_ID:
flags: object
value: 0
14 CRTC_X:
flags: signed range
values: -2147483648 2147483647
value: 0
15 CRTC_Y:
flags: signed range
values: -2147483648 2147483647
value: 0
16 CRTC_W:
flags: range
values: 0 2147483647
value: 1920
17 CRTC_H:
flags: range
values: 0 2147483647
value: 1080
10 SRC_X:
flags: range
values: 0 4294967295
value: 0
11 SRC_Y:
flags: range
values: 0 4294967295
value: 0
12 SRC_W:
flags: range
values: 0 4294967295
value: 125829120
13 SRC_H:
flags: range
values: 0 4294967295
value: 70778880
Frame buffers:
id size pitch
root@xilinx-zcu102-2025_1:/media#Refer to the Line "formats" that indicates the FrameBuffer DMA IP configuration supports XB30 VU24 XV30 YUYV XV20 BG24 GREY Y10 color formats. This setting is configured by the DMA driver device tree node property xlnx,vid-formats
DEBUG Capability
The HDMI 2.1 Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in the kernel dmesg buffer
Boards Supported
The Driver has been tested on the following boards.
ZCU102 Rev 1.1
VEK280 Rev B03
Change Log
2024.2
2024.1
2023.2
Summary:
drm: xlnx: hdmi: Removed unused hdmi->wait_for_streamup check in xlnx_…
drm: xlnx: hdmi: Fixed return value in xlnx_hdmi_exec_frl_state_lts3()
drm: xlnx: hdmi: In xlnx_hdmi_hdcp_ddc_callback_write() modify 'ret' …
drm: xlnx: hdmi: Fixed kernel documentation for xlnx_hdmi_set_frl_tmds_…
drm: xlnx: hdmi: Clear interrupt status and frl state when bridge is …
drm: xlnx: hdmi: If FRL training fails in Lts2 state, revert back to …
drm: xlnx: hdmi: Fixed kernel panic for VTC register access when link/v…
2023.1
2022.2
2022.1
2021.2
Summary:
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