The purpose of this page is to describe the Linux DRM driver for the Xilinx HDMI 2.1 TX Subsystem Soft IP for Zynq UltraScale+ MPSoC and Versal Adaptive SoC.

1 Introduction
- 1.1 HDMIPHY Interface for Zynq UltraScale+ MPSoC
- 1.2 GT PHY Interface for Versal
2 Driver Overview
3 Driver Features
4 Kernel Configuration Options for Driver
5 Device Tree Binding
6 Test procedure
- 6.1 Test procedure for video display
7 DEBUG Capability
8 Boards Supported
9 Change Log
10 Related Links

Introduction

The HDMI 2.1 Transmitter (TX) Subsystem is a feature-rich soft IP incorporating all of the necessary logic to properly interface with PHY layers and provide HDMI encoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI 2.1 TX-related IP sub-cores and outputs them as a single IP. It is an out-of-the-box ready-to-use HDMI 2.1 Transmitter Subsystem and avoids the need to manually assemble sub-cores to create a working HDMI system.

The subsystem takes incoming video and audio streams and transfers them to an HDMI stream. The stream is then forwarded to the video PHY layer.

The HDMI 2.1 Transmitter Subsystem is a MAC subsystem which works with a HDMI PHY Controller (HDMIPHY) to create a video connectivity system. The HDMI 2.1 Transmitter Subsystem is tightly coupled with the HDMIPHY Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Figure 1. Block diagram of HDMI 2.1 Tx Subsystem

HDMIPHY Interface for Zynq UltraScale+ MPSoC

The HDMI 2.1 TX Subsystem is a MAC subsystem which works with a HDMI PHY Controller (PHY) to create a video connectivity system. The HDMI 2.1 TX Subsystem is tightly coupled with the Xilinx Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Figure 2. Block diagram of MAC interface

GT PHY Interface for Versal

The HDMI 2.1 TX Subsystem is a MAC subsystem which works with a GT Controller (PHY) to create a video connectivity system. The HDMI 2.1 TX Subsystem is tightly coupled with the Xilinx GT Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Driver Overview

HDMI 2.1 TX is the last node in the display pipeline. The Linux driver is implemented as a sub-component of the Xilinx DRM KMS bridge driver and implements the encoder/connector interface. The subsystem includes the video timing generator and TX sub-core. Driver implements the DRM callbacks to read the display EDID and present it to the framework whenever a display is connected. It works in tandem with the DRM bridge driver to validate each mode listed in the EDID and reject unsupported modes.

On a mode change request from the user application, the driver works in conjunction with the DRM framework to validate the requested mode to ensure the stream can be generated by the TX core and is supported by the attached display. If the requested mode is supported, the driver will configure the TX sub-core for the new mode and the internal video timing controller (VTC) to generate the requisite video timing for it. It also configures the PHY layer for the new mode and manages all required interaction between the MAC and PHY layer.

Driver Features

IP Feature	2024.1

IP Feature	2024.1
Dynamic support of TMDS and FRL modes	Yes
Dynamic support of FRL data rate (12 Gb/s @ 4 lanes, 10 Gb/s @ 4 lanes, 8 Gb/s @ 4 lanes, 6Gb/s @ 4 lanes, 6 Gb/s @ 3 lanes, and 3 Gb/s @ 3 lanes)	Yes
Dynamic support of TMDS up to 6 Gb/s 3 lanes	Yes
Support resolutions up to 10,240 x 4,320 @ 30 fps (in FRL mode)	Tested up to 8k@60 YUV420 (in FRL mode)
Support of 8k/10kp60 YUV420 (in FRL mode)	Tested up to 8k@60 YUV420 (in FRL mode)
Support of 8, 10, 12, and 16 bits per component (BPC)	Tested 8, 10 bits per components.
Support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0 color formats.	Yes
Support 4 and 8 pixels per clock (PPC) AXI4-Stream Video input	Yes
Supports 4 pixels per clock (PPC) Native Video and Native Video (Vectored DE) input stream.	No
Supports L-PCM Audio up to 32 channels.	No
High bit rate (HBR) Audio	No
3D audio support	No
Optional HDCP 2.3/1.4 encryption support	Yes
Info frames	Yes
Data Display Channel (DDC)	Yes
Supports DDC clock stretching	Yes
Supports hot-plug detection at active-High or Low polarity	Yes
Supports HDR video transport (Dynamic Range and Mastering info frames)	No
Supports enhanced gaming and media features	No
Supports Dynamic HDR	No
Supports HDR10+ Forum VSIF	No

Kernel Configuration Options for Driver

2019.2 and later versions: Supports ONLY the new Xilinx DRM framework driver and PL crtc and can be enabled via the following configurations options: CONFIG_DRM_XLNX and CONFIG_DRM_XLNX_PL_DISP

The above defined options will only enable the new DRM framework.

Enable Xilinx HDMI 2.1 Transmitter Subsystem driver.
- 2021.2 and later versions: The HDMI 2.1 Tx driver is built as a part of the kernel, so enable the HDMI 2.1 Tx driver in the kernel configuration. Run the below command from the PetaLinux project and select "Xilinx DRM HDMI Subsystem Driver" present under “Device Drivers → Graohics support → Xilinx DRM KMS Driver” as shown below:
- $petalinux-config -c kernel

Driver source can be found at linux-xlnx/drivers/gpu/drm/xlnx/xlnx_hdmi.c at master · Xilinx/linux-xlnx (github.com)

Device Tree Binding

The DTS node should be defined with correct hardware configuration. The method to define the node is documented in

Test procedure

Test procedure for video display

HDMI-Tx can be manually configured to generate the required mode. An open-source utility like modetest can be used to configure the display pipeline.

DDR ==> FB_Rd (DMA) ==> HDMI_2.1 Tx

2021.2 and later: The Sample command to set a mode is shown below:

%> modetest -D amba_pl@0:drm-pl-disp-drv -s <connector_id>[@<crtc_id>]:<mode>[-<vrefresh>][@<format>

Example command:

%> modetest -D drm-pl-disp-drvv_hdmi_txss1 -s 38:1920x1080-60@BG24

The above command will generate a color bar pattern at the requested resolution in DDR, configure the DMA to read the frame from DDR and configure the HDMI 2.1 TX for said resolution. As a final result, the Color Bar at the defined resolution should be visible on screen.

The driver also supports changing output color formats dynamically. Available output color formats supported by DMA engine can be determined using the modetest utility as shown below:

Refer to the Line "formats" that indicates the FrameBuffer DMA IP configuration supports XB30 VU24 XV30 YUYV XV20 BG24 GREY Y10 color formats. This setting is configured by the DMA driver device tree node property xlnx,vid-formats

DEBUG Capability

The HDMI 2.1 Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in the kernel dmesg buffer

Boards Supported

The Driver has been tested on the following boards.

ZCU102 Rev 1.1
VEK280 Rev B01

Xilinx Wiki

Xilinx DRM KMS HDMI 2.1 TX Subsystem Driver

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