Xilinx V4L2 SDI Rx driver

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Last updated: Nov 18, 2021 by Vishal Sagar

Table of Contents

Introduction

The Xilinx UHD SDI Rx Subsystem consists of UHD SDI Rx IP core, an SDI to native video bridge followed by a Native to AXI-4 S bridge. It is capable of detecting the SD, HD, 3GA, 3GB, 6G and 12G (upto 8 data streams) type SDI streams. The maximum resolution it supports is 4096x2160p60 in 12G mode. The SDI Rx IP allows the configuration of the modes to be detected at run time or a fixed mode. It also allows the Framer to be enabled. A video lock event is generated when the incoming SDI mode and transport stream is detected and is stable for a configurable number of video clocks as programmed in the Video Lockout Window. When the input video stream is stopped or the type changed, a video unlock event is generated. The IP gives out the CRC and EDH error status. When the bridges are enabled, then the AXI-4 Stream of YUV 422 10 bit per component and 2 pixels per clock is sent out.



The SDI Rx Subsystem driver (xilinx-sdirxss.c) is based on the V4L2 framework.
It creates a subdev node(/dev/v4l-subdev*) which can be used to query and configure the UHD SDI Rx Subsystem IP.
The SDI Rx IP would be the first node in the video capture pipeline.
It exposes various V4L controls which can be used to configure the subsystem like auto detection of SDI modes, Framer enable, etc and query the status like CRC status, EDH errors, etc.
It also exposes certain V4L events like video unlock, bridge overflow/underflow, video source change, etc which can be used by application to trigger certain actions.
The general description of V4L2 framework is documented here, v4l2-framework.txt.

IP/Driver Features

IP feature2018.1 on wards2019.22020.12020.22021.12021.2
IP version2.0
Supports AXI4-Stream, native video and native SDI user interfacesSupports only AXI4-Stream output interface
Support for 2 pixel per sampleYes
10-bit per color componentYesAdded support for 12 bit
Supports YUV 4:2:2 and YUV 4:2:0 color spaceYes

Added support for YUV444 in IP.

Driver doesn't support

Supports YUV 420 / 422 / 444 and RGB

HFR (High Frame Rate) Support 96/1.001, 96, 100, 120/1.001 and 120 HzNANot supported in driverSupported
AXI4-Lite interface for register access to configure different subsystem optionsYes
Audio supportSeparate driver
Standards compliance
  • SMPTE ST 259: SD-SDI at 270 Mb/s.
  • SMPTE RP 165: EDH for SD-SDI.
  • SMPTE ST 292: HD-SDI at 1.485 Gb/s and 1.485/1.001 Gb/s.
  • SMPTE ST 372: Dual Link HD-SDI.
  • SMPTE ST 424: 3G-SDI with data mapped by any ST 425-x mapping at 2.97 Gb/s and 2.97/1.001 Gb/s.
  • SMPTE ST 2081-1: 6G-SDI with data mapped by any ST 2081-x mapping at 5.94 Gb/s and 5.94/1.001 Gb/s.
  • SMPTE ST 2082-1: 12G-SDI with data mapped by any ST 2082-x mapping at 11.88 Gb/s and 11.88/1.001 Gb/s.
  • Dual link and quad link 6G-SDI and 12G-SDI are supported by instantiating two or four UHD-SDI Receiver subsystems.
  • SMPTE ST 352: Payload ID packets are fully supported.
Yes*
HLG supportN.ASupported


Other driver features supported are -

  • Detect SD, HD, 3GA/3GB, 6G, 12G (upto 8 Data Streams)
  • Auto detect multiple modes OR Fixed Mode detection
  • Framer enable/disable
  • Programmable Video Lock Window
  • EDH & CRC error counters
  • Video Lock, Unlock, Bridge Over/UnderFlow interrupts
  • Separate bits to control SDI to Native and Native to AXI4-S bridge
  • ST352 Payload
  • Mode and Transport type detection
    • Fractional / Integral Frame rate
    • Interlaced / Progressive Transport
    • Family detection

Missing Features / Known Issues / Limitations in Driver

  • In case of a HD stream without payload, a progressive segmented frame (pSF) will be reported incorrectly as Interlaced as the driver relies on the IP's transport scan locked bit.
  • *Multiple instances capability not tested
  • *Tested with only 12G 8DS configuration
  • HD 1280x720p24 and HD 1280x720p23.98 - Incorrect colors are captured
  • In some 3GB 1080 modes, the colors in color bars are swapped.
  • Tested with Phabrix SDI generator and Omnitek Ultra4K
  • Doesn't support to YUV444 in 2019.2

Kernel Configuration

CONFIG_VIDEO_XILINX_SDIRXSS and CONFIG_VIDEO_XILINX should be enabled.

Device Tree Binding

The dts node should be defined with correct hardware configuration. How to define the node is documented in xlnx,sdirxss.txt

Test Procedure

The driver has been tested using the YAVTA tool.

Certain parameters like Framer enable, Video lockout window, etc can be configured using the YAVTA tool as follows -
For example, to list all the controls and current values
yavta -l /dev/v4l-subdev0

#Below is sample output when video is not locked and not streaming
root@zcu106-zynqmp:~# yavta -l /dev/v4l-subdev0
Device /dev/v4l-subdev0 opened.
--- User Controls (class 0x00980001) ---
control 0x0098ca01 `SDI Rx : Enable Framer' min 0 max 1 step 1 default 1 current 1.
control 0x0098ca02 `SDI Rx : Video Lock Window' min 0 max -1 step 1 default 12288 current 12288.
control 0x0098ca03 `SDI Rx : EDH Error Count Enable' min 0 max 65535 step 0 default 0 current 0.
control 0x0098ca04 `SDI Rx : Modes search Mask' min 0 max 63 step 0 default 63 current 63.
unable to get control 0x0098ca05: Invalid argument (22).
control 0x0098ca05 `SDI Rx : Mode Detect Status' min 0 max 5 step 1 default 0 current n/a.
control 0x0098ca06 `SDI Rx : CRC Error status' min 0 max -1 step 1 default 0 current 0.
unable to get control 0x0098ca07: Invalid argument (22).
control 0x0098ca07 `SDI Rx : EDH Error Count' min 0 max 65535 step 1 default 0 current n/a.
unable to get control 0x0098ca08: Invalid argument (22).
control 0x0098ca08 `SDI Rx : EDH Status' min 0 max -1 step 1 default 0 current n/a.
unable to get control 0x0098ca09: Invalid argument (22).
control 0x0098ca09 `SDI Rx : TS is Interlaced' min 0 max 1 step 1 default 0 current n/a.
unable to get control 0x0098ca0a: Invalid argument (22).
control 0x0098ca0a `SDI Rx : Active Streams' min 1 max 16 step 1 default 1 current n/a.
unable to get control 0x0098ca0b: Invalid argument (22).
control 0x0098ca0b `SDI Rx : Is 3GB' min 0 max 1 step 1 default 0 current n/a.
11 controls found.
Unable to get format: Inappropriate ioctl for device (25).
The SDI Rx subsystem locks on to the incoming video stream.
Using VIDIOC_SUBDEV_G_FMT ioctl, the width, height and field type (interlaced or progressive) can be determined.
The resolution info can be sent across to video capture application like YAVTA to capture the stream frames into the DDR using a simple design
SDI Rx SS ==> VDMA S2MM OR Framebuffer Write ==> Memory


For example, to capture a 1920x1080 stream the following command is used
yavta -n 3 -c10 -f YUYV -s 1920x1080 --skip 7 -F /dev/video0
The captured .bin files can then be viewed in yuvplayer.exe application.

Debug capability

The driver debug messages can be enabled by adding "#define DEBUG" at the top of the file.
All debug prints are sent to serial console and can be viewed in kernel dmesg buffer.
Some tips to help you debug are as below -
  1. The SDI source connected to SDI Rx port and should be running.
  2. The driver should have been loaded successfully during kernel bootup.
  3. Running media-ctl should show resolution.
    1. E.g. “media-ctl –d /dev/media0 –p”
  4. Always check if the lock has occurred or not.
  5. If the lock is occurred, is the current mode (SD, HD, 3GA, 3GB, 6G, 12GI or 12GF) same as source?
  6. What is the ST352 payload in RX_ST352_DATA_DS1 register? Decode it to get resolution and size and color format. 
    • Refer to driver code how to decode.
  7. Compact GT Reset - There are 2 signals connected to compact_gt which need to be toggled to have a clean reset of the GT.

    1. The SI5324_LOL should be toggled to high and then made low. (Default low)

    2. The fmc_init_done line should be toggled to low and then high (Default high).

FAQ

Q1 - While running yavta for resolution AxB with our source box, we see "Unable to start streaming: Invalid argument (22)." Why is this happening?

Ans - One possible reason is that the resolution that the SDI source is generating and what is being passed to yavta don't match.

Run media-ctl to find out the resolution currently being identified by the SDI Rx IP driver.

Read your SDI source documentation to know how to manipulate the resolutions.


Q2 - The frame rate reported by yavta is significantly lesser than expected.

Ans - Depending on your design and system load, there may be a case where there may be frame drops.

But double check the ST352 payload in SDI Rx to verify if the SDI source connected is correctly generating the required frame rate (fps).

You may have to refer to PG205 to decode the RX FAMILY to get the resolution and RX Frame Rate (in case of zero payload in 2017.3/4)


Family Detection

rx_t_familyTransport Video FormatActive Pixels
0000SMPTE ST 2751920 x 1080
0001SMPTE ST 2961280 x 720
0010SMPTE ST 2048-22048x1080
0011SMPTE ST 2951920 x 1080
1000NTSC720 x 486
1001PAL720 x 576
1111Unknown
OthersReserved


Frame Rate

rx_t_rateFrame Rate
0000None
001023.98 Hz
001124 Hz
010047.95 Hz
010125 Hz
011029.97 Hz
011130 Hz
100048 Hz
100150 Hz
101059.94 Hz
101160 Hz
OthersReserved

Q3 - After boot up, even though there is valid SDI source connected, the IP is unable to detect the source and video is not locked. Why could this happen?

Ans - Check if the IP's registers are not default values after kernel boots up. E.g. MODULE_CTRL register should be 0x3F30. If the registers are in default state, it may mean the clocking to the IP is not correct. Please check device tree to set the correct clock source.

Boards Supported

Driver has been tested on the following boards
  1. ZCU106 1.0

Known Issues

  • AR68766 - SMPTE UHD-SDI RX Subsystem - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions

Change log

2021.2

2021.1

  • Summary
    • No change

2020.2

2020.1

2019.2

  • Summary
    • Fixed driver based on comments received while upstreaming like enumerating media bus formats.
    • Fixed interrupt handling for combined lock/unlock interrupts and correctly clearing processed interrupts
  • Commits

    • 3de732f v4l: xilinx: sdirxss: Uninitialize the subsystem correctly

    • 23b13a3 v4l: xilinx: sdirxss: Check for 10bpc in dt

    • df18806 v4l: xilinx: sdirxss: Call xsdirx_streamflow_control() directly

    • 1df1d9f v4l: xilinx: sdirxss: Make functions static inline

    • 75b9c47 v4l: xilinx: sdirxss: Fix code formatting and comments

    • 4414443 v4l: xilinx: sdirxss: Correct handling of combined lock/unlock interrupts

    • 784427f v4l: xilinx: sdirxss: Clear processed interrupts only

    • 1c98050 v4l: xilinx: sdirxss: Add support to enumerate media bus formats

    • b1b4c50 v4l: xilinx: sdirxss: Replace single element array with variable

    • f3bd12b v4l: xilinx: sdirxss: Use clk_bulk_* apis

    • b996133 v4l: xilinx: sdirxss: Make structures constant

2019.1

  • Summary
    • Fixed the media bus formats to 10 bpc type (MEDIA_BUS_FMT_UYVY10_1X20 and MEDIA_BUS_FMT_VYYUYY10_4X20).
  • Commits
    • a2c1ff4 v4l: xilinx: sdirxss: Fix the media bus formats to 10bpc type

2018.3

  • Summary
    • Correct the SD 525i mode height to 486
    • Add support for clock framework
  • Commits

    • 93ac88b v4l: xilinx: sdirxss: Add support for clock framework

    • 81ae867 v4l: xilinx: sdirxss: Correct the height of SD 525i to 486

2018.2

  • Summary
    • Correct the v4l2_field to V4L2_FIELD_ALTERNATE
  • Commits
    • 11024d3 v4l: xilinx: sdirxss: Correct the v4l2_field to V4L2_FIELD_ALTERNATE

2018.1

  • Summary
    • Add support for YUV420 decoding
    • Update Video lockout Window to 32 bit
  • Commits

    • 9e963f4 v4l: xilinx: sdirxss: Add support for YUV420 decoding

    • b60524e v4l: xilinx: sdirxss: Update Video lockout Window to 32 bit

    • 818f168 Merge tag 'v4.14' into master

    • 84dcc9a v4l: xilinx: sdirxss: Remove useless semicolon

2017.4

  • Summary
    • Added V4L controls for getting transport stream type, Active streams, 3G level B
    • Added support to get frame rate
  • Commits

    • bd8f87c v4l: xilinx: sdirxss: Add V4L control for 3G Level B support

    • d9a3b95 v4l: xilinx: sdirxss: Add V4L control for Active streams

    • 79d7896 v4l: xilinx: sdirxss: Add v4l control for transport stream type

    • 3c2b606 v4l: xilinx: sdirxss: Add support for subdev get frame interval

    • 4c3b2e3 v4l: xilinx: sdirxss: Add ST352 decode macros

    • 031a2e1 v4l: xilinx: sdirxss: Decode ST352 in irq context

2017.3

  • Summary
    • Initial revision released.
  • Commits

    • 726f7831 v4l: xilinx: sdirxss: Add source change event support

    • cba7215 v4l: xilinx: sdirxss: Decode HD mode stream in case of no payload

    • 820df1b v4l: xilinx: sdirxss: Add support to decode 1080 line video in HD mode

    • f0e5fae v4l: xilinx: sdirxss: Add support to get width,height in SD mode

    • 24ed4f9 v4l: xilinx: sdirxss: Add support to decode more ST352 payloads for 3G mode

    • 4258d83 v4l: xilinx: sdirxss: Support decoding ST352 payload for 6G mode

    • 3c5133a v4l: xilinx: sdirxss: Support decoding ST352 payload for 12G mode

    • b47af26 v4l: xilinx: sdirxss: Get EDH status only in case of SD mode

    • 865daaa v4l: xilinx: sdirxss: Don't register EDH controls if EDH not enabled in IP core

    • c4258bf v4l: xilinx: sdirxss: Detect mode based on capability

    • edd5155 v4l: xilinx: sdirxss: Fix kbuild warning of variable used without initalizing

    • a5d7bad v4l: xilinx: sdirxss: Update for new register spec

    • 89a7ff0 v4l: xilinx: sdirxss: Initial support for getting video stream properties

    • eb81908 v4l: xilinx: sdirxss: Add support for Video Unlock event

    • 206948a v4l: xilinx: sdirxss: Add V4L get controls for Modes, CRC, EDH and Video Bridge Status

    • c9e6857 v4l: xilinx: sdirxss: Add V4L control for Mode detection

    • fcf25ff v4l: xilinx: sdirxss: Add V4L control for EDH error count

    • a5c2d98 v4l: xilinx: sdirxss: Add v4l control for Video Lock Window

    • 4eaea74 v4l: xilinx: sdirxss: Add v4l control for Framer

    • 6147fea v4l: xilinx: sdirxss: Streaming is enabled only on video lock

    • 5c64f19 v4l: xilinx: sdirxss: Fix xsdirxss_core for kernel-doc

    • fcdd729 v4l: xilinx: Driver support for Xilinx UHDSDI Rx subsystem

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