| | |
|---|
Yocto | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| Upgraded Yocto Rocko version from 2.4.1 to 2.4.3 Added support for meta-xilinx-tools layer to use trim version of xsct tools to build components like FSBL, PMUFW etc. Added Wayland compositor and GBM buffer management support in MALI user space libraries for 32 and 64 bit mode.
Added Device Tree Overlay support for Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC devices. Added machine conf file for ZCU111 evaluation board. Correction of NIST reported CVE(https://nvd.nist.gov/vuln/detail/CVE-2016-6301) in busybox.
|
FSBL | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| Added support for dynamic DDR Controller configuration for ZCU102 eval boards. Added support for low-density ISSI serial NOR flash for Zynq-7000, Zynq UltraScale+ MPSoCs, and RFSoC devices.
|
PMUFW (Platform Management Unit Firmware) | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| Warm Restart. Wiki doc Added OCM address map documentation required for Warm Restart. Added example for idling individual peripherals in the PL during Warm Restart. Added support for production of warm restart UC2: APU master, RPU Slave to product release.
Power Management DDR Management
Added DDR in self-refresh mode prior to PS-only restart solution. Added Zynq UltraScale+ MPSoC PS reset with DDR Data Retention.
Security Added support for accessing AES hardware to encrypt or decrypt the data blob. Provided interface to read or write efuse memory map, by default this feature is in disabled state, enable this in xpfw_config.h via "ENABLE_EFUSE_ACCESS".
Watchdog
Added FPD watchdog timer used by multi boot goes in conflict with warm restart.
Added watchdog init scripts.
Set healthy boot bit and start the watchdog during init. User executable commands to set healthy boot bit, clear healthy bootbit, start the wdt, stop the wdt and restart the wdt.
Added support for WDT Reset on timeout feature in Linux WDT driver.
|
Arm Trusted Firmware (ATF) | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| |
U-boot | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| Added support for WDT based on hooks in u-boot to pet the Watch Dog Timer for Zynq and ZynqMP Added Support for ISSI QSPI flash devices -is25lp008d (8M/3.3V), is25wp008d (8M/1.8V) -is25lp016d (16M/3.3V), is25wp016d(16M/1.8V) -is25lp032d (32M/3.3V), is25wp032d (32M/1.8V) -is25wp064d (64M/1.8V)
Added support for encryption and decryption on data blob. For more info check command help. Command: zynqmp aes <srcaddr> <ivaddr> <len> <aesop> <keysrc> <dstaddr> [keyaddr]
Added 64-bit support for ZynqMP GEM driver
Added 64-bit support for ZynqMP QSPI operations
Added support for mmio read and write commands for performing read and write to registers (For debugging only).
Added support to program SD/eMMC ITAP/OTAP tap delays by reading the values from device-tree.
Added GMMI2RGMII driver support. This converter acts as bridge between MAC and external phy MAC <==> GMII2RGMII <==> RGMII_PHY.
Added new command "zynqmp tcminit <mode>" for intializing TCM from ZynqMP u-boot
Added support for Avnet Ultra96 which is re-branded to Xilinx ZCU100 revC/D.
|
Device-tree Generation (DTG) | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| Device Tree nodes generation support for all the Multimedia IP drivers listed in description( Single path pipeline topology) MIPI CSI RX DSI TX SDI TX SDI Rx Gamm Lut Demosaic Scaler -V4L2 Color Space conversion-V4l2 Color Space conversion-DRM bridge Scaler -DRM bridge Video Mixer VTC Frame buffer Rd Frame buffer Wr I2S Tx I2S Rx SDI TX -Audio SDI RX -Audio HDMI TX -Audio HDMI Rx -Audio Audio Formatter Scene Change Detection IP
Add support for DT sub-nodes for the MAC IP when multi core is enabled ( two or more) in Vivado design. Enhancement of DTG functionality to get all PS peripherals configuration changes from PCW.
Added support for custom board dtsi files out of device tree repository.
Added generic clock support for Zynq/ZynqMP for all the PL IP's.
Added support for PS-PL configuration.
Added support for removal of PL nodes in DTG
Added mainline kernel(v4.17) device tree support
Build Device Tree Blob
|
Linux Kernel and Drivers | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| FPGA Manager Added FPGA manager support for Zynq with Full bit stream support. FPGA Manager to support setting the PS-PL configurations , example like PS-PL clock
FPGA Manager: Partial Reconfiguration Support ( Both Non-secure and Secure)
Added support for PL configuration read back Added support for clock framework Added support for Vivado generated bit and bin file loading Runtime reprogramming the PL using Full bit-stream through FPGA Manager in Linux
AXI Ethernet RFDC: Updated driver and examples to remove the xparameters.h dependency for Linux platform - This change will impact the existing Linux applications. With the new implementation, users will get all rfdc configuration data from the Linux Device tree. They don’t have to rely on xparameters.h and *_g.c files. A new API has been introduced to make this new solution work. Users have to make one extra API call XRFdc_GetDeviceNameByDeviceId() to get the RFdc device name before making a call to metal_device_open().
Updated DAC min sampling rate to 500MHz and also update VCO Range, PLL_DIVIDER and PLL_FPDIV ranges. Added XRFdc_GetFabClkOutDiv() API to read fabric clk div. Added Inline APIs XRFdc_CheckBlockEnabled(), XRFdc_CheckTileEnabled(). Added MixerType member to MixerSettings structure and Update Mixer Settings APIs to consider the MixerType variable - This change will impact the existing mixer applications. The existing entries CoarseMixMode and FineMixerMode has been merged into a single entry named MixerMode. Users must initialize the new entry MixerType and MixerMode input along with other entries in XRFdc_Mixer_Settings structure.
Added inline APIs XRFdc_CheckDigitalPathEnabled(), XRFdc_IsADCDigitalPathEnabled(), XRFdc_IsDACDigitalPathEnabled() and XRFdc_GetMultibandConfig() API to read Multiband configuration. Removed __MICROBLAZE__ defines and use libmetal interface for Microblaze - This will impact compiling RFdc driver for Microblaze. Updated powerup-state value based on PLL mode in XRFdc_DynamicPLLConfig() API. Added support to read the REFCLKDIV param from design and also updated XRFdc_SetPLLConfig() API to support range of REF_CLK_DIV values(1 to 4). Added XRFDC_MIXER_MODE_R2R option to support BYPASS mode for Real input.
QSPI ZynqMP: Added support for runtime idle. Added support for gpio cs. Added Support for ISSI QSPI flash devices -is25lp008d (8M/3.3V), is25wp008d (8M/1.8V) -is25lp016d (16M/3.3V), is25wp016d(16M/1.8V) -is25lp032d (32M/3.3V), is25wp032d (32M/1.8V) -is25wp064d (64M/1.8V)
UARTlite: UARTPS: PL353 Zynq NAND: USB ZynqMP: Fixed broken OTG HNP feature Re-enabled jumbo frame support for Ethernet over USB Fixed udc_set_speed() handling based on max_speed property
AXI USB Display Port XDMA MicroBlaze: NVMEM: CRYPTO: Register Access: |
OpenAMP and Libmetal | Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| Upgrade OpenAMP components to latest public/community release. Improved modularity of OpenAMP code base.
Added debugging remote executable loaded with OpenAMP in UG1186 documentation.
Added debugging remote executable loaded with RProc/Sysfs in UG1186 documentation.
Public Guidance Information for extended usage of OpenAMP software components in UG1186 documentation.
|
VCU (Video Codec Unit) | | Long Term Reference frame support in VCU stack( Control software, Openmax and Gstreamer). SEI information insertion in the encoded streams to be enabled in VCU stack (control SW, OMX and G-streamer).
Added Audio solution with VCU.
CCF compliance for Display Port, GPU and VCU drivers.
Dual-pass encoding feature support in VCU ( Control software, Openmax and Gstreamer).
Dynamic change of bitrate / frame rate support in VCU ( Control software, Openmax and Gstreamer).
Enhancement of Low Delay GOP Structure.
HEVC interlace support in decoder ( Control software, Openmax and Gstreamer).
HEVC interlace support in encoder ( Control software, Openmax and Gstreamer).
Linux driver for scene change detection IP. Added Scene change detection feature.
Added support for Display-less EGL rendering for MALI binaries.
Added support for PL DDR.
Added support for 32 streams of 420p.
Low Latency mode support in VCU control software.
Low latency mode support in VCU at GStreamer.
Low latency mode support in VCU at OpenMAX IL.
I2S based audio solution support with VCU.
|
QEMU | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| |
Xen | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| |
Baremetal BSP, Drivers and Libraries | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC
| freertos10_xilinx_v1_2: Updated tcl to support hierarchical designs Updated tcl to add checking for valid ticker timer Updated tcl to detect standalone version, based on the generated BSP project.
intc_v3_8: Added support for vector address greater than 32 bit. Fixed driver tcl, to detect cascaded interrupt controllers connected through irq_in port. Updated tcl to support hierarchical designs
lwip202_v1_2: mcdma_v1_2: Add API to do the lookup by the base address. Updated tcl to support hierarchical designs. In interrupt and polled example read max transfer size from IP configuration.
xxvethernet_v1_1: axivdma_v6_6: rfdc_v5_0: Updated DAC min sampling rate to 500MHz and also update VCO Range, PLL_DIVIDER and PLL_FPDIV ranges. Added XRFdc_GetFabClkOutDiv() API to read fabric clk div. Added Inline APIs XRFdc_CheckBlockEnabled(), XRFdc_CheckTileEnabled(). Added MixerType member to MixerSettings structure and Update Mixer Settings APIs to consider the MixerType variable - This change will impact the existing mixer applications. The existing entries CoarseMixMode and FineMixerMode has been merged into a single entry named MixerMode. Users must initialize the new entry MixerType and MixerMode input along with other entries in XRFdc_Mixer_Settings structure.
Added inline APIs XRFdc_CheckDigitalPathEnabled(), XRFdc_IsADCDigitalPathEnabled(), XRFdc_IsDACDigitalPathEnabled() and XRFdc_GetMultibandConfig() API to read Multiband configuration. Removed __MICROBLAZE__ defines and use libmetal interface for Microblaze - This will impact compiling RFdc driver for Microblaze. Updated powerup-state value based on PLL mode in XRFdc_DynamicPLLConfig() API. Added support to read the REFCLKDIV param from design and also updated XRFdc_SetPLLConfig() API to support range of REF_CLK_DIV values(1 to 4). Added XRFDC_MIXER_MODE_R2R option to support BYPASS mode for Real input.
scugic_v3_10: standalone_v6_8: Added support for 64 bit variant of microblaze processor. Updated CortexR5 BSP to initialize CortexR5 core with LOVEC Optimized cache APIs in CortexA53 64 bit BSP Updated tcl to support hierarchical designs Updated CortexA9 translation table, to fix issue related to OpenAMP use case.
tmrctr_v4_5: ttcps_v3_7: xilfpga_v4_2: Added support for readback of PL configuration data. Added support to load the vivado generated .bit and .bin files. Added Example for loading partial reconfiguration bitstreams. Modified the PL data handling Logic to support different PL programming interfaces. Added support for unaligned bitstream programming. Fixed issues with secure partial bitstream loading.
usbpsu_v1_4 Added composite gadget support standalone and freertos Added DFU example for freertos Added Mass Storage example for freertos Added Keyboard example for freertos Added Audio example for freertos
qspipsu_1_8: Added support for the ISSI flash parts: IS25LP080D (8M/3.3V), IS25WP080D (8M/1.8V), IS25LP016D (16M/3.3V), IS25WP016D (16M/1.8V), IS25LP032D (32M/3.3V), IS25WP032D (32M/1.8V), IS25LP064A (64M/3.3V), and IS25WP064A (64M/1.8V)
qspips_3_5: Added support for the ISSI flash parts: IS25LP080D (8M/3.3V), IS25WP080D (8M/1.8V), IS25LP016D (16M/3.3V), IS25WP016D (16M/1.8V), IS25LP032D (32M/3.3V), IS25WP032D (32M/1.8V), IS25LP064A (64M/3.3V), and IS25WP064A (64M/1.8V)
canfd_1_2: pciepsu_v1_0: Added support for PS PCIe root complex standalone driver. Enumerate End points in PCIe hierarchy. Assign BAR's to end points.
nandpsu_1_8: |