2018.3 Release Notes for Open Source Components

This page provides details on the 2018.3 release information such as new features and bug fixes for all the Xilinx Open Source Components. 

New Features

Component Name
Platform/SoC Supported
Feature Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Upgraded Yocto Rocko version from 2.4.1 to 2.4.3
  • Added support for meta-xilinx-tools layer to use trim version of xsct tools to build components like FSBL, PMUFW etc.
  • Added Wayland compositor and GBM buffer management support in MALI user space libraries for 32 and 64 bit mode.
  • Added Device Tree Overlay support for Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC devices.
  • Added machine conf file for ZCU111 evaluation board.
  • Correction of NIST reported CVE(https://nvd.nist.gov/vuln/detail/CVE-2016-6301) in busybox.
FSBL
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Added support for dynamic DDR Controller configuration for ZCU102 eval boards.
  • Added support for low-density ISSI serial NOR flash for Zynq-7000, Zynq UltraScale+ MPSoCs, and RFSoC devices.
PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Warm Restart. Wiki doc
    1. Added OCM address map documentation required for Warm Restart.
    2. Added example for idling individual peripherals in the PL during Warm Restart.

    3. Added support for production of warm restart UC2: APU master, RPU Slave to product release.

  • Power Management
    • Added documentation for how idle peripherals are handled through Vivado and PMU subsystem configuration.
    • Added support to check FPD lockout condition.
  • DDR Management
    1. Added DDR in self-refresh mode prior to PS-only restart solution.
    2. Added Zynq UltraScale+ MPSoC PS reset with DDR Data Retention.
  • Security
    • Added support for accessing AES hardware to encrypt or decrypt the data blob.
    • Provided interface to read or write efuse memory map, by default this feature is in disabled state, enable this in xpfw_config.h via "ENABLE_EFUSE_ACCESS".
  • Watchdog
    1. Added FPD watchdog timer used by multi boot goes in conflict with warm restart.
    2. Added watchdog init scripts.
      1. Set healthy boot bit and start the watchdog during init.
      2. User executable commands to set healthy boot bit, clear healthy bootbit, start the wdt, stop the wdt and restart the wdt.
    3. Added support for WDT Reset on timeout feature in Linux WDT driver.
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
U-boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Added support for WDT based on hooks in u-boot to pet the Watch Dog Timer for Zynq and ZynqMP
  • Added Support for ISSI QSPI flash devices -is25lp008d (8M/3.3V), is25wp008d (8M/1.8V) -is25lp016d (16M/3.3V), is25wp016d(16M/1.8V) -is25lp032d (32M/3.3V), is25wp032d (32M/1.8V) -is25wp064d (64M/1.8V)
  • Added support for encryption and decryption on data blob. For more info check command help. Command: zynqmp aes <srcaddr> <ivaddr> <len> <aesop> <keysrc> <dstaddr> [keyaddr]
  • Added 64-bit support for ZynqMP GEM driver
  • Added 64-bit support for ZynqMP QSPI operations
  • Added support for mmio read and write commands for performing read and write to registers (For debugging only).
  • Added support to program SD/eMMC ITAP/OTAP tap delays by reading the values from device-tree.
  • Added GMMI2RGMII driver support. This converter acts as bridge between MAC and external phy MAC <==> GMII2RGMII <==> RGMII_PHY.
  • Added new command "zynqmp tcminit <mode>" for intializing TCM from ZynqMP u-boot
  • Added support for Avnet Ultra96 which is re-branded to Xilinx ZCU100 revC/D.
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Device Tree nodes generation support for all the Multimedia IP drivers listed in description( Single path pipeline topology)
    1. MIPI CSI RX
    2. DSI TX
    3. SDI TX
    4. SDI Rx
    5. Gamm Lut
    6. Demosaic
    7. Scaler -V4L2
    8. Color Space conversion-V4l2
    9. Color Space conversion-DRM bridge
    10. Scaler -DRM bridge
    11. Video Mixer
    12. VTC
    13. Frame buffer Rd
    14. Frame buffer Wr
    15. I2S Tx
    16. I2S Rx    
    17. SDI TX -Audio
    18. SDI RX -Audio    
    19. HDMI TX -Audio
    20. HDMI Rx -Audio
    21. Audio Formatter
    22. Scene Change Detection IP
  • Add support for DT sub-nodes for the MAC IP when multi core is enabled ( two or more) in Vivado design.
  • Enhancement of DTG functionality to get all PS peripherals configuration changes from PCW.
  • Added support for custom board dtsi files out of device tree repository.
  • Added generic clock support for Zynq/ZynqMP for all the PL IP's.
  • Added support for PS-PL configuration.
  • Added support for removal of PL nodes in DTG
  • Added mainline kernel(v4.17) device tree support
  • Build Device Tree Blob
Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC

FPGA Manager

  • Added FPGA manager support for Zynq with Full bit stream support.
  • FPGA Manager to support setting the PS-PL configurations , example like PS-PL clock
  • FPGA Manager: Partial Reconfiguration Support ( Both Non-secure and Secure)
  • Added support for PL configuration read back 
  • Added support for clock framework 
  • Added support for Vivado generated bit and bin file loading
  • Runtime reprogramming the PL using Full bit-stream through FPGA Manager in Linux

AXI Ethernet 

  • Split dma and MCDMA programming sequence in separate sources.

RFDC:

  • Updated driver and examples to remove the xparameters.h dependency for Linux platform - This change will impact the existing Linux applications.
    • With the new implementation, users will get all rfdc configuration data from the Linux Device tree. They don’t have to rely on xparameters.h and *_g.c files. A new API has been introduced to make this new solution work.
    • Users have to make one extra API call XRFdc_GetDeviceNameByDeviceId() to get the RFdc device name before making a call to metal_device_open().
  • Updated DAC min sampling rate to 500MHz and also update VCO Range, PLL_DIVIDER and PLL_FPDIV ranges.
  • Added XRFdc_GetFabClkOutDiv() API to read fabric clk div.
  • Added Inline APIs XRFdc_CheckBlockEnabled(), XRFdc_CheckTileEnabled().
  • Added MixerType member to MixerSettings structure and Update Mixer Settings APIs to consider the MixerType variable - This change will impact the existing mixer applications.
    • The existing entries CoarseMixMode and FineMixerMode has been merged into a single entry named MixerMode.
    • Users must initialize the new entry MixerType and MixerMode input along with other entries in XRFdc_Mixer_Settings structure.
  • Added inline APIs XRFdc_CheckDigitalPathEnabled(), XRFdc_IsADCDigitalPathEnabled(), XRFdc_IsDACDigitalPathEnabled() and XRFdc_GetMultibandConfig() API to read Multiband configuration.
  • Removed __MICROBLAZE__ defines and use libmetal interface for Microblaze - This will impact compiling RFdc driver for Microblaze.
    • RFdc driver with Microblaze in baremetal must also enable Libmetal library while configuring the standalone BSP.
  • Updated powerup-state value based on PLL mode in XRFdc_DynamicPLLConfig() API.
  • Added support to read the REFCLKDIV param from design and also updated XRFdc_SetPLLConfig() API to support range of REF_CLK_DIV values(1 to 4).
  • Added XRFDC_MIXER_MODE_R2R option to support BYPASS mode for Real input.

QSPI ZynqMP:

  • Added support for runtime idle.
  • Added support for gpio cs.
  • Added Support for ISSI QSPI flash devices -is25lp008d (8M/3.3V), is25wp008d (8M/1.8V) -is25lp016d (16M/3.3V), is25wp016d(16M/1.8V) -is25lp032d (32M/3.3V), is25wp032d (32M/1.8V) -is25wp064d (64M/1.8V)

UARTlite:

  • Added support for dynamic allocation of the serial ids.

UARTPS:

  • Added support for dynamic allocation of the serial ids.

PL353 Zynq NAND:

  • Added support for ECC checking for on-die flashes.
  • Added support for De selection of chip select

USB ZynqMP:

  • Fixed broken OTG HNP feature
  • Re-enabled jumbo frame support for Ethernet over USB
  • Fixed udc_set_speed() handling based on max_speed property

AXI USB

  • Added suspend/ resume support for axi usb

Display Port

  • Extend DRM Driver support for allocating buffers from reserved memory space.

XDMA MicroBlaze:

  • Added support for XDMA bridge RP driver to MicroBlaze architecture.
  • Supports BAR assignment.
  • Supports Legacy & MSI interrupts. 

NVMEM:

  • Provided support to access(read/write) non-volatile efuse memory through NVMEM framework

CRYPTO:

  • Added support for encryption or decryption of data blobs using AES hardware engine.

Register Access:

  • Provided sysfs interface /sys/firmware/zynqmp/config_reg to access CSU/PMU global registers
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Upgrade OpenAMP components to latest public/community release.
  • Improved modularity of OpenAMP code base.
  • Added debugging remote executable loaded with OpenAMP in UG1186 documentation.
  • Added debugging remote executable loaded with RProc/Sysfs in UG1186 documentation.
  • Public Guidance Information for extended usage of OpenAMP software components in UG1186 documentation.
VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC
  • Long Term Reference frame support in VCU stack( Control software, Openmax and Gstreamer).
  • SEI information insertion in the encoded streams to be enabled in VCU stack (control SW, OMX and G-streamer).
  • Added Audio solution with VCU.
  • CCF compliance for Display Port, GPU and VCU drivers.
  • Dual-pass encoding feature support in VCU ( Control software, Openmax and Gstreamer).
  • Dynamic change of bitrate / frame rate support in VCU ( Control software, Openmax and Gstreamer).
  • Enhancement of Low Delay GOP Structure.
  • HEVC interlace support in decoder ( Control software, Openmax and Gstreamer).
  • HEVC interlace support in encoder ( Control software, Openmax and Gstreamer).
  • Linux driver for scene change detection IP.
  • Added Scene change detection feature.
  • Added support for Display-less EGL rendering for MALI binaries.
  • Added support for PL DDR.
  • Added support for 32 streams of 420p.
  • Low Latency mode support in VCU control software.
  • Low latency mode support in VCU at GStreamer.
  • Low latency mode support in VCU at OpenMAX IL.
  • I2S based audio solution support with VCU.
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None.
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Upgraded to Xen version 4.11
  • Added cacheable Shared Memory between Linux and Bare-metal guests.
Baremetal BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC

freertos10_xilinx_v1_2:

  • Updated tcl to support hierarchical designs 
  • Updated tcl to add checking for valid ticker timer
  • Updated tcl to detect standalone version, based on the generated BSP project.

intc_v3_8:

  • Added support for vector address greater than 32 bit.
  • Fixed driver tcl, to detect cascaded interrupt controllers connected through irq_in port.
  • Updated tcl to support hierarchical designs 

lwip202_v1_2:

  • Added mcdma support
  • Added 2.5G PL Ethernet support
  • Updated tcl to support hierarchical designs 

mcdma_v1_2:

  •  Add API to do the lookup by the base address.
  • Updated tcl to support hierarchical designs.
  • In interrupt and polled example read max transfer size from IP configuration.

xxvethernet_v1_1:

  • Add API's to do the lookup by the base address and MCDMA helper functions.

axivdma_v6_6:

  • Add vertical flip programming support.

rfdc_v5_0:

  • Updated DAC min sampling rate to 500MHz and also update VCO Range, PLL_DIVIDER and PLL_FPDIV ranges.
  • Added XRFdc_GetFabClkOutDiv() API to read fabric clk div.
  • Added Inline APIs XRFdc_CheckBlockEnabled(), XRFdc_CheckTileEnabled().
  • Added MixerType member to MixerSettings structure and Update Mixer Settings APIs to consider the MixerType variable - This change will impact the existing mixer applications.
    • The existing entries CoarseMixMode and FineMixerMode has been merged into a single entry named MixerMode.
    • Users must initialize the new entry MixerType and MixerMode input along with other entries in XRFdc_Mixer_Settings structure.
  • Added inline APIs XRFdc_CheckDigitalPathEnabled(), XRFdc_IsADCDigitalPathEnabled(), XRFdc_IsDACDigitalPathEnabled() and XRFdc_GetMultibandConfig() API to read Multiband configuration.
  • Removed __MICROBLAZE__ defines and use libmetal interface for Microblaze - This will impact compiling RFdc driver for Microblaze.
    • RFdc driver with Microblaze in baremetal must also enable Libmetal library while configuring the standalone BSP.
  • Updated powerup-state value based on PLL mode in XRFdc_DynamicPLLConfig() API.
  • Added support to read the REFCLKDIV param from design and also updated XRFdc_SetPLLConfig() API to support range of REF_CLK_DIV values(1 to 4).
  • Added XRFDC_MIXER_MODE_R2R option to support BYPASS mode for Real input.

scugic_v3_10:

  • Fixed interrupt id computation for vectored interrupts
  • Updated tcl to support hierarchical designs 

standalone_v6_8:

  • Added support for 64 bit variant of microblaze processor.
  • Updated CortexR5 BSP to initialize CortexR5 core with LOVEC  
  • Optimized cache  APIs in CortexA53 64 bit BSP
  • Updated tcl to support hierarchical designs 
  • Updated CortexA9 translation table, to fix issue related to OpenAMP use case.

tmrctr_v4_5:

  • Added support for PWM
  • Updated applications to call TmrCtrDisableIntr with correct arguments.

ttcps_v3_7:

  • Fixed XTtcPs_CalcIntervalFromFreq API to use correct maximum interval count for zynqMP

xilfpga_v4_2: 

  • Added support for readback of PL configuration data.
  • Added support to load the vivado generated .bit and .bin files.
  • Added Example for loading partial reconfiguration bitstreams.
  • Modified the PL data handling Logic to support different PL programming interfaces.
  • Added support for unaligned bitstream programming.
  • Fixed issues with secure partial bitstream loading.

usbpsu_v1_4

  • Added composite gadget support standalone and freertos
  • Added DFU example for freertos
  • Added Mass Storage example for freertos
  • Added Keyboard example for freertos
  • Added Audio example for freertos

qspipsu_1_8:

  • Added support for the ISSI flash parts: IS25LP080D (8M/3.3V), IS25WP080D (8M/1.8V), IS25LP016D (16M/3.3V), IS25WP016D (16M/1.8V), IS25LP032D (32M/3.3V), IS25WP032D (32M/1.8V), IS25LP064A (64M/3.3V), and IS25WP064A (64M/1.8V)

qspips_3_5:

  • Added support for the ISSI flash parts:  IS25LP080D (8M/3.3V), IS25WP080D (8M/1.8V), IS25LP016D (16M/3.3V), IS25WP016D (16M/1.8V), IS25LP032D (32M/3.3V), IS25WP032D (32M/1.8V), IS25LP064A (64M/3.3V), and IS25WP064A (64M/1.8V)

canfd_1_2: 

  • Added support for canfd 2.0 spec.

pciepsu_v1_0:

  • Added support for PS PCIe root complex standalone driver.
  • Enumerate End points in  PCIe hierarchy.
  • Assign BAR's to end points. 

nandpsu_1_8:

  • Added Support 64 bit DMA addresses for Microblaze-X

xilisf:

  • Added support for the ISSI flash parts:  IS25LP080D (8M/3.3V), IS25WP080D (8M/1.8V), IS25LP016D (16M/3.3V), IS25WP016D (16M/1.8V), IS25LP032D (32M/3.3V), IS25WP032D (32M/1.8V), IS25LP064A (64M/3.3V), and IS25WP064A (64M/1.8V)
  • Added support for MX66U1G45G and MX66L1G45G flash parts from Macronix of size 1G
  • Added support for MT25QL01G(1G/3V) and MT25QL02G(2G/3V) flash parts from Micron

Bug Fixes

Component Name
Platform/SoC Supported
Bug Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • sysroot unable to export qmake path
  • 2018.1 ZynqMP VCU TRD PetaLinux BSP doesn't build with PetaLinux/Yocto SDK generation
  • Yocto/PetaLinux doesn't build when ATF DEBUG is enabled
  • Disabling Busybox utilities in yocto/petalinux
FSBL
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Zynq UltraScale+ MPSoC FSBL not checking all RSA Enable eFuses.

  • Zynq UltraScale+ MPSoC FSBL bug for secure bitstream on PS only reset.

  • ZCU104 FSBL Errors on boot.

  • Zynq UltraScale+ MPSoC DDR test failed when setting auto self-refresh.

  • Samsung DDR4 requirement of Temp Controlled Refresh Rate.
  • Routine in psu_ddr_phybringup_data Overwriting Original Value in PGCR2.
  • PS DDR - psu_init.c should stop on PLL and calibration errors.
  • Zynq UltraScale+ MPSoC PSW for DDR configurations does not have Refresh mode settings for DDR3/DDR3L//LPDDR3/LPDDR4.
  • Need to review ZDDR settings related to power saving in half-width mode.
PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Request for Power off suspend to DDR bare metal application.

  • Linux PM debugfs doesn't work.

  • Idle peripherals before PS and System warm restart.

Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None
U-boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • eMMC probe failed: -95 because of bug in get_timer().

  • Fix misaligned buffer address when saving envvars to FAT.

  • Zynq UltraScale+ MPSoC unable to erase-verify or write-verify S25FL256SAGBHID10 in X1-Single mode.

Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • While building Getting device tree error when we add 100G ethernet IP core to design, because of 64-bit value.

  • DTG build errors with AXI DMA Clock nodes.

  • Incorrect interrupt id's being generated in the pl.dtsi.

  • Clock wizard speed grade property error.

  • Syntax error from system.mss when generating dtg bsp from SDK.

  • Incorrect device tree node generated for axi vdma with single frame buffer.

Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Zynq UltraScale+ MPSoC RSA Driver crashs when data received is less than 512 bytes

  • AXI IIC Linux driver missing bytes while reading from slave.

  • Zynq UltraScale+ MPSoC mtd_debug in I/O mode leads high CPU utilization to impact custom system's behavior.

  • Linux JFFS2 kernel panic on POR or reboot.

  • Macb driver fix for rx bd increment sequence to avoid memory issues.

  • Macb driver - fix PTP time adjustment for large negative delta.
  • Macb driver - fixes for power management and phy & mdio error condition handling. 
  • Zynq UltraScale+ MPSoC AXI GPIO driver probe report "gpio-keys" errors

  • Zynq UltraScale+ MPSoC Unable to mount jffs2 filesystem while booting from QSPI (mt25qu02g ) flash

  • ZCU102 Rev D1/Rev1.1 board - SPI Full-duplex interrupt does does not occurs correctly.

  • ZCU106 SI570 clock registration failed.

  • USB3.0 Ethernet gadget Jumbo frame cannot be sent.

  • Zynq-7000 added support for flash part IS25LP128

  • UBI ECC error on S34ML02G1

  • Zynq-7000 Wake on UART is broken.

  • Incorrect use of __flush_cache_user_range in zynqmp_fpga_ops_write

  • xilinx-ams: vccaux11 outputs 3 times the expected voltage.

  • Zynq UltraScale+ MPSoC DisplayPort Controller Linux Driver does not support both the live input and the DP DMA input as the same time.

  • Zynq UltraScale+ MPSoC DisplayPort Controller Linux Driver always assumes that the DisplayPort output (GTRs) will be used.

  • DMA engine drivers (AXIDMA, VDMA, and CDMA) - Reset DMA channel in dma_terminate_all and fix 64-bit simple CDMA transfer.

OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Cleanup/Additional information needed in UG1186.

  • fread() returns the number of units have been read.

  • Synchronous External Abort with zynqmp_r5_remoteproc.

  • Observed remoteproc error in dmesg on Zynq-7000 devices.

VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC
  • VCU Control Software Decoder Example App Hangs with Long Picture Delays.

  • Recording AVC baseline/high profile not working.

  • VCU Control Software Decoder Example App Hangs with Delayed Picture.

  • QP values not being set when QPCtrlMode set to LOADQP or LOAD_QP | RELATIVE_QP.

  • VCU Control Software Encoder Example App Output Buffer size should be based on bitrate requirements.

  • Video quality degraded with LOW_LATENCY mode.

  • VCU control software fail to release memory after encoding.

  • Unable to get DMABUF buffer from Decoder --> APPSink.

  • Encoder Ports not flushed on Seek event in GStreamer application.

  • Observed DMA fd import issue when video crop element is used in the pipeline.

  • OMX Decoder application doesn't work.

  • Provide (PTS) metadata structure to decoder.

  • I-Frame Flickering Effect with Lower CPBSize

  • Reduce the I-frame from 500KB to 100KB.

  • VCUcontrol software crash when performing multiple concurrent transcoding tasks.

  • VCU sets a lot more Macro blocks to intra or inter-prediction mode instead of skip mode when compared to x264.

  • VCU TRD bitrate overshoot when using VBR.

QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • ZCU102 QSPI Boot mode.
  • QEMU binaries built from github repo throws gdb connection timeout issue in tap mode.
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None
Baremetal BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fix for MicroBlaze_sleep in FreeRTOS.

  • DPDMA Example doesn't work on ZCU102 board.

  • Zynq UltraScale+ MPSoC Unable to program bitstream using Xilfpga Library example.

  • Time out error is not handled in master mode standalone drivers.

  • Zynq UltraScale+ MPSoC USB3.0 Hot plug won’t work if USB cable is disconnected during bulk transfer.

  • SDK HDF does not show all address ranges for custom IP.

  • VCU118 Eeprom example doesn't work in SDK.

  • Zynq MPSoC DRAM Test - Running Eye Test Back to Back Seems to Cause a Partial Init of the Controller and reports Read Eye and Read Centering Error.

  • AXI INTC driver does not detect cascaded AXI Interrupt Controllers.

  • XilSecure library doesn't clear user key.

  • XilSecure library doesn't clear user key.

  • Zynq UltraScale+ MPSoC DRAM tests issues found when run write eye test in loop.
  • Zynq UltraScale+ MPSoC DRAM test read eye width is shrinking and AUTO CENTER value mismatches EYE CENTER after thousands of loops.
  • No fallback performed after XFSBL_ERROR_SYSTEM_WDT_RESET.
  • SD read failed when multiple FreeRTOS tasks read from SD card simultaneously.
  • RPU project getting corrupted if imported along with bsp.
  • Zynq UltraScale+ MPSoC DRAM tests fail with Hynix DDR4.
  • Linux call to Sha3Update() fails if payload is not 4 bytes aligned.
  • XSecure_Sha3Update() fails if payload is not 4 bytes aligned.
  • Update Zynq DRAM Diagnostics Tests for Full Memory Range Coverage.
  • Zynq UltraScale+ MPSoC XilFPGA secure does not compile on A53 or R5 bare metal.
  • Zynq-7000 AMP use case the translation table entries (for DDR) are incorrect
  • Peripheral test with multiple timer instances.
  • Zynq-7000 DDRless Flash programming does not work.
  • Xilsf operations at address 0.
  • eFUSE Program Strobe width doc mismatch.
  • XilRSA library documentation.
  • BlockErase for Spansion devices.
  • Possible uninitialized FlashImageOffsetAddress
  • Wrong check for the partition present device in xfsbl_image_header.c
  • Zynq UltraScale+ MPSoC ILA probes on interrupts signals generates different interrupt vectors in xparameters.h
  • Please add Macronix flash in XILSF.
  • Zynq UltraScale+ MPSoC Linux AES Access GCM tag mismatch causes segfault.
  • LWIP - fix phy management for emaclite.
  • CANFD - Fixed the incorrect updation of tx buffer when using message Que.
  • Xilisf: Fixed the address address for block and erase, as they can have non-zero addresses

Related Links