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Yocto | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Use O2 instead of Os compiler optimization for barmetal toolchain libraries to improve performance regression observed with memcpy() Issue warning message in petalinux project if devtool workspace is on NFS mount which results in increased time to launch u-boot or linux menuconfig
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FS-Boot Zynq-7000 FSBL Zynq UltrsScale+ FSBL | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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PMUFW (Platform Management Unit Firmware) | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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PLM (Platform Loader and Manager) | | |
Arm Trusted Firmware (ATF) | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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U-Boot | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Use nfs when the file to be tftp'ed is bigger than 90MB. Nand write failed due to Flash issue on the board. Provided flash block protection using lock/unlock feature as a patch. Support is added for S25FL256Lxxx U-boot is able to boot from the env stored in mmc, it was not an issue. QSPI feedback clock needs to be enabled to work at above 40Mhz. So for mini u-boot change the operating frequency to 40Mhz to work irrespective of the feedback clock. For systems with multiple memory nodes with addresses above 39bits and below 39bits, find the first memory node with address below 39bits and use it for relocating. skipping baud_rate_val calculation wrong issue was not reproducible on xilinx boards Use itest in place of test command for using -gt, -lt, -eq, -ge, -le, -ne qualifiers.
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Device-tree Generation (DTG) | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| When there is only one memory mapped axi external interface in the PL (no other PL IP present), it fails to find the bus_node. Fix this by adding the external interfacing under the root node. When multiple ethernet cores are present in the design and these cores are connected to the axi_dma IP, clocks and interrupts are incorrectly generated. Fixed this by correctly updating the clocks and interrupts along with the existing ethernet clocks. DTG fails to generate the device nodes when the design contains multiple similar video pipelines. Implemented a way to generate all the video pipeline nodes when the design consists of multiple video pipelines. MIPI CSI Rx driver probe fails when the VCX is disabled. Fixed by adding the vc property in the device tree node. When there are external axi interface with multiple segments DTG failed to generate. There can be design with external interfaces with multiple segments and can have the same handle for them. This can create duplicate label issue. Fix this by incrementing the handle for each segment. CCI and SMMU entries are enabled in the DT, even though the xsa doesn't contain these. As these are fixed IPs they need to disable the kernel configuration. Fix the warning message "couldn't find the phydev". Looked the DTG generated node and this is in sync with the Linux driver Documentation and no change is required.
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Linux Kernel and Drivers | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| SD/eMMC tuning was failing at very low temperatures. This has been fixed by changing the tap delay settings and following the TRM properly (DLL assert->ITAP->OTAP->DLL de-assert) instead of the previous flow (DLL assert->ITAP->DLL de-assert->DLL assert->OTAP->DLL de-assert) mmc tuning failure was observed for UHS mode in SD boot. In UHS mode (SDR104), ITAP val should be programmed to zero by Linux driver which was not happening (resulting in using older tap values programmed by fsbl). This has been fixed in this release. In the Xilinx DMA driver the DMA transfer might finish just after checking the state with dma_cookie_status, but before the lock is acquired. Not checking for empty list in xilinx_dma_tx_status may result in reading random or corrupted data when the descriptor is wriiten to. This has been fixed in this release. smbus_block_read is added to the Xilinx AXI IIC driver to read from few sensors which support this command. In the Zynq SOC it is observed that under heavy stress at times even though all the data is received, timeout error may occur. This is because of a known IP bug because of which the COMP bit in ISR is not getting set at the end of transfer for certain conditions. A SW workaround was already provided which was not working for one particular use case. The SW workaround is to clear the HOLD bit before the transfer size register reaches '0'. The current implementation clears the HOLD bit only for the use case where data to be received is less than FIFO DEPTH. It does not handle the use case where data to be received is equal to FIFO DEPTH.
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OpenAMP and Libmetal | Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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VCU (Video Codec Unit) | | Incorrect POC for skip frames in encoder encoding is fixed. Fixed omx-decoder application (qnx) for output buffer re-order issue when Bframes count is greather than 1. Decoder error stream concealment is improved. NTSC 480i encode and decode support is added DMAfd reference count issue fixed in sample gstreamer application for appsrc to omxh264enc use-case Fixed PSNR drop with increased bitrate issue with adjusting encoder max-picture-size config setting. Fixed race condition in customer omx application while reading the input YUV frame Added XB30 video format support for Gstreamer
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QEMU | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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Xen | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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BSP, Drivers and Libraries | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| The user config option of use_task_fpu_support as 2 was not working as expected for A53/A72 based FreeRTOS BSPs. It has been fixed now. This option ensures that each and every FreeRTOS task saves and restores the floating point/neon registers. In R5 FreeRTOS BSP support for properly handling Undefined Exception handler was missing. This has been fixed in this release. The AXI I2C BM NAS handler used to flush the Tx FIFO unconditionally. It has been fixed now. To take care of high traffic condition it is always desired to check for NAS condition once again inside the NAS handler before flushing the FIFO. For HW designs where an axiethernet is not connected to a DMA, the driver tcl throws an error. Though it is always desirable to connect a DMA to an ethernet, an error from tcl and failure in generation of a platform is not desirable. This has been fixed in this release. Zynq Ultrascale+ SDIO solution does not support MicroSD card connectors that have opposite polarity of Card Detect switch. There is no SW solution for the same. An AR https://www.xilinx.com/support/answers/75375.html was created to explain the same to customer and provide an alternate HW based solution. One of the emaclite driver examples "xemaclite_internal_loopback_example" was not getting pulled up in Vitis because of a bug in the dependencies.prop file. This issue has been fixed in this release. A bug in the lwIP emacps adapter where the wrong count was used while freeing of rx pbufs is fixed in this release. An issue in the ddrpsv driver tcl has been fixed because of which under certain conditions incorrect base/high addresses were getting generated. The emaclite driver had a bug in the function XEmacLite_AlignedWrite where it was using an incorrect pointer type. It is fixed in this release. The existing SD driver had a bug where it was reading 32 bit from the block size register which was of 16bits. It is fixed in this release. In the AXI DMA driver a bug has been fixed because of which MM2S and S2MM Max transfer Length in function XAxiDma_CfgInitialize was being wrongly calculated for AXI DMA Micro mode. A compilation issue in xxvethernet driver example has been fixed which was being caused because of incorrect conditional compilation condition.
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