2020.2 Release Notes for Open Source Components

This page provides details on the 2020.2 release information such as new features and bug fixes for all the Xilinx Open Source Components. 

Table of Contents

New Features

Component Name
Platform/SoC Supported
Feature Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Addition of Vitis AI 1.2.1
  • Update to qemu 5.0
  • Binary distribution and package based on zynq/zynqmp/versal generic machines available on petalinux.xilinx.com
  • Infrastructure for asynchronous update feed
  • Addition of Alveo card management controller (CMC) package
  • Updates in fpgamanager* classes
  • Additions/updates around system controller apps

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None

PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None
PLM (Platform Loader and Manager)
  • Versal
  • OSPI dual stacked support
  • Image store support for warm restart use cases
  • PLM WDT support
  • Parallel DMA for QSPI and OSPI cases
  • 64 bit support for OSPI, DDR(SRC), SD
  • Parallel DMA support for XilLoader
  • Madagascar: Unique id support

  • Boot time estimator (Secure cases)

  • Secure debug basic support
  • Glitch detection related features
  • 128 bit AES key support
  • ECDSA P-521 curve support
  • AIE clock gating at boot
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Adding the EM specific SMC handler for the EM-related requests.
  • Check for DLL status before doing reset.
  • Disable ITAPDLYENA bit for zero ITAP delay.
  • Add support of set max latency for the device
  • Add support to get clock rate value.
  • Add support of register notifier.
U-Boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • AXI Ethernet support on Versal
  • AXI UART support on Versal
  • OSPI dual Stacked mode support in U-boot.
  • Secure full bitstream loading support
  • Secure Linux and rootfs loading support
  • ISSI and Giga device OSPI part support in U-boot.
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Proper Representation of multimedia Video Pipelines IPs in DTG.
  • Added mainline kernel versions support from v5.0 – v5.4 in DTG.
  • Added support for DP Tx and DP Rx IPs.
  • Enable Support for the Deephi DPU.
  • Added the gpio interrupt controller support in cascade scenario.
  • Added support for Versal PL PCIe.
  • Added Sysmon IP support for Versal.
Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • DFx AXI shutdown manger driver support in Kernel
  • AXI Ethernet support on Versal
  • MRMAC 10G support on Versal
  • Linuxdriver support of Softip’s for Versal platform.
    • AXI GPIO
    • AXI IIC,
    • AXI CAN/CANFD
    • AXi Traffic generator
    • AXI INTC
    • AXI watchdog
  • ISSI and Gigadevice OSPI part support in Linux.
  • OSPI Stacked mode support in Linux.
  • Window watchdog Linux driver support for Versal
  • Versal EDAC driver support for DDR.
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Upgrade to 2020.04 upstream OpenAMP release.
  • VFIO libmetal driver
VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC
  • HDR10 is supported for capture, VCU encode/decode and display at gstreamer level
  • Added max-consecutive-skip parameter to VCU encoder.
  • Interlace video support added for SCD MM.
  • NTSC 4:2:0 interlace support is added to VCU encoder/decoder.
  • Interlace audio/video support is validated.
  • xAVC profile compliance is verified.
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • USB Support (Host Mode)
  • CAN & CAN-FD Support
  • Based on Mainline QEMU 5.0
  • Overhaul of UG1160 to a New Web Based Format.
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • 1:1 memory mappings for Xen virtual machines, enabling device assignments without SMMU
  • Static assignment of PL blocks, including bus-mastering blocks, to Xen virtual machines
  • Direct assignment of the AIE array to Xen virtual machines
BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Enhance PS-PL interrupt handling in Baremetal to support concat and slices in the path.
  • DFx AXI shutdown manger driver support in baremetal
  • Updated Makefiles to support parallel make and reduce build time.
  • Enabled Support for Creating Virtualized (EL1) FreeRTOS applications in Vitis
  • New example application to demonstrate use of interrupts in FreeRTOS applications
  • BareMetal  driver support of Softip’s for Versal platform.
    • AXI GPIO
    • AXI IIC
    • AXI CAN/CANFD
    • AXi Traffic generator
    • AXI watchdog
  • ISSI and Gigadevice OSPI part support in BareMetal
  • OSPI Dual-Stacked mode support in BareMetal
  • Versal USB hibernation support in BareMetal driver
  • XilFPGA library to support loading of both secure(except KUP key) and nonsecure bitstreams(PDI) for Versal.
  • Baremetal AXI Ethernet driver support for Versal.
AI Engine(AIE)
  • Versal* (AI Core Series)
  • AIE v2 Driver with Linux Kernel driver support
  • Error reporting in linux
  • Block RTP update
  • ECC Scrubbing 
  • Enhanced Clock Gating
  • Application termination and rerun ( without rebooting)

Bug Fixes

Component Name
Platform/SoC Supported
Bug Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Use O2 instead of Os compiler optimization for barmetal toolchain libraries to improve performance regression observed with memcpy()
  • Issue warning message in petalinux project if devtool workspace is on NFS mount which results in increased time to launch u-boot or linux menuconfig

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Fix in Zynq-7000 FSBL to detect QSPI size over 1Gb.
PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Disable PMU scan-enable in PMUFW source code (though user documentation says so, this was not actually done in code earlier).
PLM (Platform Loader and Manager)
  • Versal
  • To address the ES1 issue that SRST will not work if the Sysmon clock source is not IRO, PLM is updated (for ES1 only) to change the clock source to IRO before issuing a SRST. 
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Provide the capability to handle EM module in the ATF. Added the new smc handler for EM module.
U-Boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Use nfs when the file to be tftp'ed is bigger than 90MB. 
  • Nand write failed due to Flash issue on the board.
  • Provided flash block protection using lock/unlock feature as a patch.
  • Support is added for S25FL256Lxxx
  • U-boot is able to boot from the env stored in mmc, it was not an issue.
  • QSPI feedback clock needs to be enabled to work at above 40Mhz. So for mini u-boot change the operating frequency to 40Mhz to work irrespective of the feedback clock.
  • For systems with multiple memory nodes with addresses above 39bits and below 39bits, find the first memory node with address below 39bits and use it for relocating. 
  • skipping baud_rate_val calculation wrong issue was not reproducible on xilinx boards
  • Use itest in place of test command for using -gt, -lt, -eq, -ge, -le, -ne qualifiers.
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • When there is only one memory mapped axi external interface in the PL (no other PL IP present), it fails to find the bus_node. Fix this by adding the external interfacing under the root node.
  • When multiple ethernet cores are present in the design and these cores are connected to the axi_dma IP, clocks and interrupts are incorrectly generated. Fixed this by correctly updating the clocks and interrupts along with the existing ethernet clocks.
  • DTG fails to generate the device nodes when the design contains multiple similar video pipelines. Implemented a way to generate all the video pipeline nodes when the design consists of multiple video pipelines.
  • MIPI CSI Rx driver probe fails when the VCX is disabled. Fixed by adding the vc property in the device tree node.
  • When there are external axi interface with multiple segments DTG failed to generate. There can be design with external interfaces with multiple segments and can have the same handle for them. This can create duplicate label issue. Fix this by incrementing the handle for each segment.
  • CCI and SMMU entries are enabled in the DT, even though the xsa doesn't contain these. As these are fixed IPs they need to disable the kernel configuration.
  • Fix the warning message "couldn't find the phydev". Looked the DTG generated node and this is in sync with the Linux driver Documentation and no change is required.
Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • SD/eMMC tuning was failing at very low temperatures. This has been fixed by changing the tap delay settings and following the TRM properly (DLL assert->ITAP->OTAP->DLL de-assert) instead of the previous flow (DLL assert->ITAP->DLL de-assert->DLL assert->OTAP->DLL de-assert)

  • mmc tuning failure was observed for UHS mode in SD boot. In UHS mode (SDR104), ITAP val should be programmed to zero by Linux driver which was not happening (resulting in using older tap values programmed by fsbl). This has been fixed in this release.

  • In the Xilinx DMA driver the DMA transfer might finish just after checking the state with dma_cookie_status, but before the lock is acquired. Not checking for empty list in xilinx_dma_tx_status may result in reading random or corrupted data when the descriptor is wriiten to. This has been fixed in this release.

  • smbus_block_read is added to the Xilinx AXI IIC driver to read from few sensors which support this command.
  • In the Zynq SOC it is observed that under heavy stress at times even though all the data is received, timeout error may occur. This is because of a known IP bug because of which the COMP bit in ISR is not getting set at the end of transfer for certain conditions. A SW workaround was already provided which was not working for one particular use case. The SW workaround is to clear the HOLD bit before the transfer size register reaches '0'. The current implementation clears the HOLD bit only for the use case where data to be received is less than FIFO DEPTH. It does not handle the use case where data to be received is equal to FIFO DEPTH.

OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal

VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC 
  • Incorrect POC for skip frames in encoder encoding is fixed.
  • Fixed omx-decoder application (qnx) for output buffer re-order issue when Bframes count is greather than 1.
  • Decoder error stream concealment is improved.
  • NTSC 480i encode and decode support is added
  • DMAfd reference count issue fixed in sample gstreamer application for appsrc to omxh264enc use-case
  • Fixed PSNR drop with increased bitrate issue with adjusting encoder max-picture-size config setting.
  • Fixed race condition in customer omx application while reading the input YUV frame 
  • Added XB30 video format support for Gstreamer 
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal

Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal

BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • The user config option of use_task_fpu_support as 2 was not working as expected for A53/A72 based FreeRTOS BSPs. It has been fixed now. This option ensures that each and every FreeRTOS task saves and restores the floating point/neon registers.
  • In R5 FreeRTOS BSP support for properly handling Undefined Exception handler was missing. This has been fixed in this release.
  • The AXI I2C BM NAS handler used to flush the Tx FIFO unconditionally. It has been fixed now. To take care of high traffic condition it is always desired to check for NAS condition once again inside the NAS handler before flushing the FIFO.
  • For HW designs where an axiethernet is not connected to a DMA, the driver tcl throws an error. Though it is always desirable to connect a DMA to an ethernet, an error from tcl and failure in generation of a platform is not desirable. This has been fixed in this release.
  • Zynq Ultrascale+ SDIO solution does not support MicroSD card connectors that have opposite polarity of Card Detect switch. There is no SW solution for the same. An AR https://www.xilinx.com/support/answers/75375.html was created to explain the same to customer and provide an alternate HW based solution.
  • One of the emaclite driver examples "xemaclite_internal_loopback_example" was not getting pulled up in Vitis because of a bug in the dependencies.prop file. This issue has been fixed in this release.
  • A bug in the lwIP emacps adapter where the wrong count was used while freeing of rx pbufs is fixed in this release.
  • An issue in the ddrpsv driver tcl has been fixed because of which under certain conditions incorrect base/high addresses were getting generated.
  • The emaclite driver had a bug in the function XEmacLite_AlignedWrite where it was using an incorrect pointer type. It is fixed in this release.
  • The existing SD driver had a bug where it was reading 32 bit from the block size register which was of 16bits. It is fixed in this release.
  • In the AXI DMA driver a bug has been fixed because of which MM2S and S2MM Max transfer Length in function XAxiDma_CfgInitialize was being wrongly calculated for AXI DMA Micro mode. 
  • A compilation issue in xxvethernet driver example has been fixed which was being caused because of incorrect conditional compilation condition.
  • A bug in the xttcps_intr_example is fixed in this release where settings for tick and PWM timer needed to be swapped for expected behavior.
  • A bug in the mutex driver tcl is fixed because of which canonical definitions where getting generated incorrectly for designs where multiple mutex IPs are present.
  • An issue for the use case where multiple packets are sent in interrupt mode has been fixed.
  • An AR has been created to mention that the existing xilflash library does not support the flash part Micron (MT28EW01GABA1HJS).
  • Avoidable delay in OSPI driver while checking for done bit through a sleep of 1 msec has been reduced to a sleep of 1 micro sec. This makes the transfer much faster.
  • A bug in the AXI SPI/AXI QSPI driver is fixed. Because of this issue the driver keeps on filling the txfifo till the txfifo_full condition is set. However, this condition never occurs as the data gets pushed out as soon it is written into the fifo. The driver as a result of this over fills the txfifo resulting in rx fifo overrun. 

  • It was observed that Axi qspi transfer fails when opted for a transaction width is 16 bit. The issue is not because of the driver or the IP, but because of the flash parts not reconnizing 16 bit transfers. It was obsrved that there are no easily available flash parts that can suppoprt 16 bit transfer.

  • An issue was observed where on Versal specific boards (e.g. VCK190) upon POR, uboot and Linux both were detecting invalid PHY addresses. This was because TI PHY present on these boards reads a resistor grid on board upon POR and deciphers its own PHY address value and this resistor grid's signals are driven through MIOs which, depending on the time it takes during/after bootROM, can drive some garbage values. The issue is fixed by making appropriate changes in Vivado board file.

  • In the lwIP code base a bug exists for Zynq based use cases. Because of this if a design has only GEM1 the slcr divisors used for clock settings will get wrong. This issue has been fixed.
  • GIC and INTC driver tcls have been updated to support various use cases through which an interrupt can be connected. Users can decided to use slices, concat blocks and other similar logics to connect interrupts. The previous implementation of GIC and INTC driver tcls were not supporting the same and it was resulting in wrong interrupt id generation.
  • In Zynq MP DRAM Diagnostic Test issue has been fixed in random value generation logic in the memtest.
  • The existing R5 MPU handling has a bug because of which it does not remember or store the static MPU regions already created during the bootup sequence. This means, users can override the static MPU regions that are already created as part of the R5 MPU design. This is fixed in this release
  • A bug has been fixed where the some part of lwIP code was resulting in security violation. Some part of lwIP adapter code was directly accessing registers through pointers instead of going through standard and safe Xil_Out32 and XIl_In32 way. The issue has been fixed in this release.
  • In the lwIP code base 6-Wire SGMII mode on the DP83867 is now enabled prior to DMA initialization. In the earlier code base without this change it was resulting in an unresponsive PCS/PMA IP.
  • The existing lwIP adapter code base, because of a bug there are corner case chances where a BS used bit might get cleared with a NULL buffer address. This has been fixed in this release.
  • The Zynq Ultrascale+ MPSoC DRAM test application was not using DRAM VRef Range for 2D Write Eye Test. This is fixed in this release.
  • Fix for misleading return value from a XilSKey function (XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc)
  • Deprecate support of Versal Family Key

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