When there is only one memory mapped axi external interface in the PL (no other PL IP present), it fails to find the bus_node. Fix this by adding the external interfacing under the root node.
When multiple ethernet cores are present in the design and these cores are connected to the axi_dma IP, clocks and interrupts are incorrectly generated. Fixed this by correctly updating the clocks and interrupts along with the existing ethernet clocks.
DTG fails to generate the device nodes when the design contains multiple similar video pipelines. Implemented a way to generate all the video pipeline nodes when the design consists of multiple video pipelines.
MIPI CSI Rx driver probe fails when the VCX is disabled. Fixed by adding the vc property in the device tree node.
When there are external axi interface with multiple segments DTG failed to generate. There can be design with external interfaces with multiple segments and can have the same handle for them. This can create duplicate label issue. Fix this by incrementing the handle for each segment.
CCI and SMMU entries are enabled in the DT, even though the xsa doesn't contain these. As these are fixed IPs they need to disable the kernel configuration.
Fix the warning message "couldn't find the phydev". Looked the DTG generated node and this is in sync with the Linux driver Documentation and no change is required.
SD/eMMC tuning was failing at very low temperatures. This has been fixed by changing the tap delay settings and following the TRM properly (DLL assert->ITAP->OTAP->DLL de-assert) instead of the previous flow (DLL assert->ITAP->DLL de-assert->DLL assert->OTAP->DLL de-assert)
mmc tuning failure was observed for UHS mode in SD boot. In UHS mode (SDR104), ITAP val should be programmed to zero by Linux driver which was not happening (resulting in using older tap values programmed by fsbl). This has been fixed in this release.
In the Xilinx DMA driver the DMA transfer might finish just after checking the state with dma_cookie_status, but before the lock is acquired. Not checking for empty list in xilinx_dma_tx_status may result in reading random or corrupted data when the descriptor is wriiten to. This has been fixed in this release.
smbus_block_read is added to the Xilinx AXI IIC driver to read from few sensors which support this command.
In the Zynq SOC it is observed that under heavy stress at times even though all the data is received, timeout error may occur. This is because of a known IP bug because of which the COMP bit in ISR is not getting set at the end of transfer for certain conditions. A SW workaround was already provided which was not working for one particular use case. The SW workaround is to clear the HOLD bit before the transfer size register reaches '0'. The current implementation clears the HOLD bit only for the use case where data to be received is less than FIFO DEPTH. It does not handle the use case where data to be received is equal to FIFO DEPTH.
The user config option of use_task_fpu_support as 2 was not working as expected for A53/A72 based FreeRTOS BSPs. It has been fixed now. This option ensures that each and every FreeRTOS task saves and restores the floating point/neon registers.
In R5 FreeRTOS BSP support for properly handling Undefined Exception handler was missing. This has been fixed in this release.
The AXI I2C BM NAS handler used to flush the Tx FIFO unconditionally. It has been fixed now. To take care of high traffic condition it is always desired to check for NAS condition once again inside the NAS handler before flushing the FIFO.
For HW designs where an axiethernet is not connected to a DMA, the driver tcl throws an error. Though it is always desirable to connect a DMA to an ethernet, an error from tcl and failure in generation of a platform is not desirable. This has been fixed in this release.
Zynq Ultrascale+ SDIO solution does not support MicroSD card connectors that have opposite polarity of Card Detect switch. There is no SW solution for the same. An AR https://www.xilinx.com/support/answers/75375.html was created to explain the same to customer and provide an alternate HW based solution.
One of the emaclite driver examples "xemaclite_internal_loopback_example" was not getting pulled up in Vitis because of a bug in the dependencies.prop file. This issue has been fixed in this release.
A bug in the lwIP emacps adapter where the wrong count was used while freeing of rx pbufs is fixed in this release.
An issue in the ddrpsv driver tcl has been fixed because of which under certain conditions incorrect base/high addresses were getting generated.
The emaclite driver had a bug in the function XEmacLite_AlignedWrite where it was using an incorrect pointer type. It is fixed in this release.
The existing SD driver had a bug where it was reading 32 bit from the block size register which was of 16bits. It is fixed in this release.
In the AXI DMA driver a bug has been fixed because of which MM2S and S2MM Max transfer Length in function XAxiDma_CfgInitialize was being wrongly calculated for AXI DMA Micro mode.
A compilation issue in xxvethernet driver example has been fixed which was being caused because of incorrect conditional compilation condition.
A bug in the xttcps_intr_example is fixed in this release where settings for tick and PWM timer needed to be swapped for expected behavior.
A bug in the mutex driver tcl is fixed because of which canonical definitions where getting generated incorrectly for designs where multiple mutex IPs are present.
An issue for the use case where multiple packets are sent in interrupt mode has been fixed.
An AR has been created to mention that the existing xilflash library does not support the flash part Micron (MT28EW01GABA1HJS).
Avoidable delay in OSPI driver while checking for done bit through a sleep of 1 msec has been reduced to a sleep of 1 micro sec. This makes the transfer much faster.
A bug in the AXI SPI/AXI QSPI driver is fixed. Because of this issue the driver keeps on filling the txfifo till the txfifo_full condition is set. However, this condition never occurs as the data gets pushed out as soon it is written into the fifo. The driver as a result of this over fills the txfifo resulting in rx fifo overrun.
It was observed that Axi qspi transfer fails when opted for a transaction width is 16 bit. The issue is not because of the driver or the IP, but because of the flash parts not reconnizing 16 bit transfers. It was obsrved that there are no easily available flash parts that can suppoprt 16 bit transfer.
An issue was observed where on Versal specific boards (e.g. VCK190) upon POR, uboot and Linux both were detecting invalid PHY addresses. This was because TI PHY present on these boards reads a resistor grid on board upon POR and deciphers its own PHY address value and this resistor grid's signals are driven through MIOs which, depending on the time it takes during/after bootROM, can drive some garbage values. The issue is fixed by making appropriate changes in Vivado board file.
In the lwIP code base a bug exists for Zynq based use cases. Because of this if a design has only GEM1 the slcr divisors used for clock settings will get wrong. This issue has been fixed.
GIC and INTC driver tcls have been updated to support various use cases through which an interrupt can be connected. Users can decided to use slices, concat blocks and other similar logics to connect interrupts. The previous implementation of GIC and INTC driver tcls were not supporting the same and it was resulting in wrong interrupt id generation.
In Zynq MP DRAM Diagnostic Test issue has been fixed in random value generation logic in the memtest.
The existing R5 MPU handling has a bug because of which it does not remember or store the static MPU regions already created during the bootup sequence. This means, users can override the static MPU regions that are already created as part of the R5 MPU design. This is fixed in this release
A bug has been fixed where the some part of lwIP code was resulting in security violation. Some part of lwIP adapter code was directly accessing registers through pointers instead of going through standard and safe Xil_Out32 and XIl_In32 way. The issue has been fixed in this release.
In the lwIP code base 6-Wire SGMII mode on the DP83867 is now enabled prior to DMA initialization. In the earlier code base without this change it was resulting in an unresponsive PCS/PMA IP.
The existing lwIP adapter code base, because of a bug there are corner case chances where a BS used bit might get cleared with a NULL buffer address. This has been fixed in this release.
The Zynq Ultrascale+ MPSoC DRAM test application was not using DRAM VRef Range for 2D Write Eye Test. This is fixed in this release.
Fix for misleading return value from a XilSKey function (XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc)