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2021.2 Release Notes for Open Source Components

2021.2 Release Notes for Open Source Components

May 30, 2024

This page provides details on the 2021.2 release information such as new features and bug fixes for all the Xilinx Open Source Components. 

Table of Contents

New Features

Note:

  • Each "Component Name" has a link to respective pages. For more details refer individual pages.

Component Name

Platform/SoC Supported

Feature Description

Component Name

Platform/SoC Supported

Feature Description

Yocto

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Include Vitis AI 1.4

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Added Multidie read support for QSPI in FSBL for Zynq Ultrascale+

PMUFW (Platform Management Unit Firmware)

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Added support for overlay config object loading

  • Added support for dynamic enablement for board specific features

  • Add support for dynamic loading of config object.

  • Add IOCTL call support in PMUFW.

  • Add support for runtime feature configuration for OT.

  • Add runtime support for External WDT.

  • Add min and max limit checks for OT and External WDT features.

PLM (Platform Loader and Manager)

  • Versal

  • Added support for CPU idle during force power down

  • Added support for CPU idle during subsystem restart from PLM

  • Added support to extract metaheader of user PDIs during run-time.

  • Added support for CPM5 QDMA reset sequence

  • Added support for IPI channel prioritization

  • Code optimization/cleanup to reduce PLM size.

  • Reduce error log in slave boot modes in case of error.

  • Added prints to display secure state by default.

  • Added support for Winbond QSPI flash.

  • Added support for Macronix OSPI flash.

  • Support to disable the Auth JTAG after a user provided timeout.

  • Support added for MJTAG workaround in PLM.

  • Renamed error node ID and event ID for better clarity.

  • Support to configure UART during run-time.

  • Updated IRO frequency to 400Mhz for MP, HP parts.

  • Add support for registering error callback function to be called when a task missed execution.

  • Support for handling CPM_NCR and link-down errors.

  • Support for PROC command.

  • Display warning when APU IPI interrupts are disabled.

  • Added support to selectively disable different housecleaning functions for each power domain

Secure Libraries and Drivers

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Added support for TRNG baremetal driver (trngpsv) for Versal

  • Added client support for XilNVM library (for BBRAM and eFUSE)

  • Added BBRAM Linux driver support for Versal

  • Added 64-bit address support for XilSecure server APIs.

Arm Trusted Firmware (ATF)

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Versal: Added support to handle CPU idle during force power down callback

  • ZynqMP: Added support for dynamic feature enablement

  • Versal): Added support for SLS mitigation

  • Zynqmp: Add get feature config support

U-Boot

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Versal: Added support for PL MRMAC driver(10G & 25G configurations)

  • ZynqMP: Added support for 10G/25G(XXV) AXI ethernet driver

  • ZynqMP/Versal: Added support for Winbond qspi flash W25H02JV

Device-tree Generation (DTG)

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • axis_switch: Add support for axis_switch IP.

  • rfdc: Add DAC coupling parameter.

  • framebuf_rd/wr: Add support for 3 planar YUV 8bpc.

  • Fix the ref_clk and pl_alt_ref_clk for versal.

  • axi_ethernet: Update the fifo properties for xxv ethernet.

  • common: Update the versal clocks as per CIPS 3.0

  • ddrpsv: Fix the reg property "size" when it is 64-bit.

  • Add support for the PTP 1588 Timer Syncer IP.

  • Add config option to set buad rate.

  • Check the IP has get_mem_ranges for processor.

  • gamma: Fix the instance name passed to get the IP_NAME.

 

Linux Kernel and Drivers

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • ZynqMP Firmware: Added support for dynamic feature enablement

  • media: Add HDMI 2.1 TX subsystem

  • media: Add DP audio support

  • media: Add xhdmiphy driver

  • media: Add FRL support to hdmirx

  • media: Add Versal support for DPTX

  • dwc3: Enable D3 power state

  • dwc3: Add remove wakeup support

  • clocking-wizard: Add support for higher frequency accuracy

  • i2c: xiic: Add SCL frequency configuration support

OpenAMP and Libmetal

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • remoteproc trace buffer

    The Cortex-R5 firmware build with Vitis/Vivado now saves its runtime messages into a remoteproc trace buffer. The firmware’s resource table communicates the buffer address and size to Linux kernel. The remoteproc exports this buffer via debugFS and it can be viewed by reading /sys/kernel/debug/remoteproc/remoteproc0/trace0

  • libmetal shared memory API
    The libmetal shared memory user API based on ION interface was removed due to "Destaging ION" in the Linux kernel. For more information, please see https://lwn.net/Articles/792733/.
    The current API in Xilinx libmetal repository matches the upstream.

VCU (Video Codec Unit)

  • Zynq UltraScale+ MPSoC

  • Added support of StartCode bytes aligned mode

QEMU

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Versal: Add Sysmon sensor value injection

  • Versal: Add model of Sysmon satellites

  • Versal: DMA: Add support for runtime switching of Secure/NS transactions

  • Versal: Add MBIST and scan clearing

  • SMMU: Address translation fixes

  • SMMU: Announce ATO support in ID regs

Xen

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Secure Boot support in Xen and ImageBuilder: sign your binaries and use ImageBuilder to create a boot script that loads and verifies the signatures in U-Boot

  • ImageBuilder: support for creating disk images with multiple partitions, one for each VM with a rootfs

  • PVCalls support in Linux: an incredibly fast PV protocol for VM-to-VM communications

BSP, Drivers and Libraries

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • XilPM library: ZynqMP: Added IOCTL support for dynamic feature enablement

AI Engine(AIE)

  • Versal* (AI Core Series)

 

Bug Fixes

Note:

  • Each "Component Name" has a link to respective pages. For more details refer individual pages.

Component Name

Platform/SoC Supported

Bug Description

Component Name

Platform/SoC Supported

Bug Description

Yocto

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Fix FSBL and PMU firmware build issue for ZU67DR device

  • Update kernel offset and load address for aarch64 to avoid warning of misaligned kernel image

  • Init scripts are now able to echo to console

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

Zynq UltraScale+ FSBL:

  • Mark DDR as memory just after ECC initialization to avoid speculative accesses

  • Add support for delayed enumeration of DFU device.

  • Fix logical issue in Secondary boot mode.

  • Reset SHA engine in failure cases in authentication plus encryption cases.

PMUFW (Platform Management Unit Firmware)

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Do not turn off FPD when USB wakeup source is enabled as USB controller uses GT from FPD.

  • Handle APU restart gracefully if copying FSBL to DDR is failed.

 

PLM (Platform Loader and Manager)

  • Versal

  • Reduced 16K of reserved PPU1 RAM space for USER CODE to zero.

  • Print PLM banner at the very beginning.

  • Issue internal POR for VPK1802 ES1 devices to sync slave SLRs.

  • Fix issue in clearing CFI and CFU errors.

  • Fix secondary boot issue in SD when multiboot offset is non zero.

  • Skip providing ack for force power-down command.

Secure libraries and drivers

  • Versal

  • Zynq UltraScale+ MPSoC

xilsecure:

  • Added 64-bit address support for XilSecure server APIs.

  • Updated validation for AAD size to check if it is quad-word aligned.

  • Added EXPORT CONTROL eFuse check in all crypto init functions for ZynqMP and Versal.

  • Renamed XSecure_AesPmcDmaCfgByteSwap API with XSecure_AesPmcDmaCfgAndXfer.

  • Updated check for Size in Client XSecure_AesKekDecrypt.

  • Added check for DecKeySrc in Client XSecure_AesKekDecrypt.

xilnvm:

  • Added client-server support for BBRAM and eFUSE.

  • Added most restrictive range checks for device temperature before programming eFuses.

  • Removed clearing the BBRAM User Data in case of failure.

  • Changed PLM and Data Partition IV formatting to LE in xilnvm_efuse_versal_server_example.

  • Updated validation to check for Trim2 instead of Trim 3 for protection bit 37.

  • Added check to see if efuse bit is already programmed before programming.

Arm Trusted Firmware (ATF)

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • fix (plat/versal): do not clear ipi status for init suspend callback.

  • fix(plat/versal): Use common callback type for core and subsystem.

  • zynqmp: pm_service: Sync IOCTL IDs.

  • plat: xilinx: zynqmp: Add feature config support in IOCTL.

  • xilinx: versal: use sync method for blocking calls

U-Boot

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • ZynqMP/Versal: Fix qspi low frequency(<12.5Mhz) write issues.

  • Versal: Fix usb host issue in accessing flash drive.

  • Versal: Fix watch dog driver to use basic WWDT mode.

  • ZynqMP/Versal: Fix Quad Enable bit not getting set for upper flash in dual parallel configuration.

  • Versal: Fix duplicate memory range issue in device tree

Device-tree Generation (DTG)

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • emacps: Fix the phy node with overlay enabled.

  • MB: Generate the cpus node with single core.

  • axi_mcdma: Add the dma-cells property for the mcdma.

  • Generate the endpoints for the axis_switch memory mapped IP.

  • Fix the ref_clk and pl_alt_ref_clk for versal.

  • axi_ethernet: Update the fifo properties for xxv ethernet.

  • ddrpsv: Fix the reg property "size" when it is 64-bit.

  • ZynqMP: Check the IP has get_mem_ranges for processor.

  • gamma: Fix the instance name passed to get the IP_NAME.

Linux Kernel and Drivers

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • nand: Fix NVDDR issue

  • pinctrl: Replace io-standard property by power-source

  • zynq-gqspi: Fix tapdelay programming

  • dwc3: Fix OTG driver

  • dwc3: Fixed common regulator for multiple controller instance

  • net: In MCMDA designs fix crash on ifconfig up

  • xilinx-ai-engine: Fix requesting runtime resource bitmap setting

  • ll_temac: Fix TX BD buffer overwrite

  • spi: spi-cadence: Fix SPI CS gets toggling sporadically

  • xilinx-ai-engine: fix memory leak for resource manager

OpenAMP and Libmetal

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

libmetal: remove excessive warnings when reading UIO memory maps

VCU (Video Codec Unit) / Multimedia 

  • Zynq UltraScale+ MPSoC 

  • Fixed frameskip feature issues

  • Scheduler fixes

QEMU

  • MicroBlaze

  • Zynq-7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  •  

Xen

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal