2024.1 Release Notes for Open Source Components
This page provides details on the 2024.1 release information such as new features and bug fixes for all of the AMD Open Source Components.
New Features
Each "Component Name" has a link to respective pages. For more details refer to individual pages.
Component Name | Platform/SoC Supported | Feature Description |
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Zynq, ZynqMP, MicroBlaze, Versal, Versal Net
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Zynq, ZynqMP, MicroBlaze, Versal, Versal Net
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ZynqMP, Versal , Versal Net
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Versal Net / Versal / Zynq UltraScale+
Versal Net / Versal
Versal Net
Versal
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Zynq, ZynqMP, MicroBlaze, Versal, Versal Net
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Zynq, ZynqMP, MicroBlaze, Versal , Versal Net
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Versal , Versal Net |
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Zynq, ZynqMP, Versal, Versal Net |
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ZynqMP, MicroBlaze, Versal , Versal Net |
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ZynqMP, Versal, Versal Net |
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Versal, Versal Net | Versal
Versal Net
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Versal |
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Zynq, ZynqMP, MicroBlaze, Versal , Versal Net
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ZynqMP, Versal, Versal Net
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ZynqMP, Versal
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Versal, Versal Net |
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ZynqMP, Versal |
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ZynqMP |
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PL Connectivity Video IPs(capture) | ZynqMP, Versal |
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Bug Fixes
Each "Component Name" has a link to respective pages. For more details refer to individual pages.
Component Name | Platform/SoC Supported | Bug Description |
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| Resolved build failures for xczu67dr_SE designs Resolved QSPI FIT image issue for KCU105 .
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Documentation | Resolved the incorrect tip for Kernel debugging.
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Trusted Firmware-A (TF-A)(old name Arm Trusted Firmware (ATF))
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| XilSKey (Zynq 7000, Zynq UltraScale+):
XilSecure:
XilNVM:
XilPUF:
XilOCP (Versal Net):
XilCert (Versal Net): | |
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| Zynq UltraScale+ FSBL:
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| Zynq UltraScale+ Image Selector for SOM:
Zynq UltraScale+ Image Recovery for SOM: Versal Image Selector:
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| - Optimized the GT bus hold time (releasing the GT arbitration immediately after reading GT registers)
- In previous releases, for SSIT client interface user needs to define "XILSEM_ENABLE_SSIT " macro. Now, from this release, updated XilSEM Vitis build scripts to enable the SSIT macro automatically based on device type.
- Added protection for error injection operations in XilSEM examples with "XILSEM_ERRINJ_ENABLE". This is mainly to avoid using the example as is in the user application
- In Vitis SDT flow, event notifications are not sent to user applications from PLM due to incorrect IPI base address macro. Fixed this notification issue by correcting the base address in SDT flow.
- Added an interface to read Total frames in CRAM for SSIT devices
- Fix XilSEM enable macros in VP1902 | |
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Versal |
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GPU |
| None |
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