Component Name | Platform/SoC Supported | Bug Description |
Yocto | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Fixed recipetool create command with local file path option. Fixed SOM FRU utility to read CC MAC addresses. Removed ultra96 MIPI device tree files from meta-layer as it causes build issue for non MIPI designs. Fixed print message from daemon script which doesn't make it to Linux prompt. Fixed build throwing error prints in external network while PREMIRRORS set to downloads. Made openamp-fw packages board specific Yocto generated boot.bin for Zynq UltraScale+ MPSoC/RFSoC hangs while loading bitstream. Removed bitstream dependency in fpga-manager-util recipes when XSA does not contain bitstream. Fixed BIF_PARTITION_ATTR paths for Zynq-7000 FSBL, U-Boot and device-tree components. Fixed pl-custom.dtsi relative path build issue. Backported iproute2 patches to make it to work in 5.15 kernel.
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FS-Boot Zynq-7000 FSBL Zynq UltraScale+ FSBL | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Zynq UltraScale+ FSBL: Zynq-7000 FSBL: |
PMUFW (Platform Management Unit Firmware) | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Fix for pin ctrl issue related to bank1-ctrl5 register Fixed SOM related build flag issues Cleanup of dynamic feature config logic Overlay config object permission related fixes Provided compile time option to enable DDR XMPU entries, which would be enabled when either DDR is accessible to PMU or user explicitly enables ENABLE_DDR_XMPU macro when DDR is not accessible to PMU.
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PLM (Platform Loader and Manager) | | Fixed ROM boot time as reported during Boot time numbers printing in PLM. Fix is to use 32MHz IRO frequency while calculating ROM boot time. Fix to enable iomodule interrupts after registering iomodule handler to avoid PLM hanging if interrupt occurs before registering the iomodule. Fixed code in sleepTaskDispatchLoop by moving enable_mb_interrupts after the sleep. This is to avoid any non-determinism. Fixed the error case in which for Add ImageStore command, the same existing PDI address is passed again. Fix to ensure that AuthFailCounter is incremented only when either of the two eFUSEs AUTH_JTAG_LOCK_DIS_1_0 is programmed. Fixed by calling XPlmi_EmInit after XPlm_PmInit to clear all the PL and NOC related errors without re-occurring (which are triggered during SRST). Removed checking of the SSIT errors during synchronization between SLRs in SSIT devices. Fixed DMA keyhole issue when commands starts at the 32K boundary. Removed hardcoding of PSM RAM address for proc reserved memory. Fixed issues with loading checksum enabled partitions from DDR. Added support to change IRO frequency to 320MHZ while running PUF operation and then set back to 400MHZ. This is to add PUF support for -MP, -HP devices too. Fixed issue with copy to memory when authentication, encryption or both of them are enabled. Fix to make sure that PLM application wizard checks for all pre-requisites (required libraries). Enabled A72 elf to run from TCM when the estimation address of ELF lies in the TCM range. Fixed input validation for XPlmi_MemCpy64. Fixed Partial PDI load issue from SMAP in SSIT case by ensuring SbiRecovery API is only called when PdiSrc is JTAG or SBI JTAG. Fixed logic in XPlmi_MemSet to avoid Divide by Zero exception.
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Secure libraries and drivers | Versal Zynq UltraScale+ MPSoC
| XilNVM: Add the check to program RegInitDis bit in XilNVM examples. XilNVM: Fixed the condition resulting in exception in XilNvm_WritePufasUserFuses. XilPUF: Fix to enable XilPuf encrypt/decrypt example builds without need for any further code changes by default.
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Trusted Firmware-A(TF-A)(old name Arm Trusted Firmware (ATF)) | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Increased the max xlat tables when debug build is enabled feat(plat/zynqmp): Disabled the -mbranch-protection flag fix(plat/xilinx/zynqmp): Added UART1 as console fix (plat/xilinx/zynqmp): Used common interface for EEMI APIs fix(Versal) : Resolved misra issues fix(xilinx): Fixed mismatching function prototype plat: zynqmp: Fixed coverity scan warnings plat: versal: Fixed coverity scan warnings
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U-Boot | Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| ZynqMP/Versal: Fixed quad enable issue of Winbond flashes for second flash in dual stacked configuration . ZynqMP/Versal: Fixed issue of not booting when CONFIG_ENV_IS_IN_SPI_FLASH is disabled in QSPI boot mode. Zynq/ZynqMP/Versal: Fixed issue of read/write in Flashes with <16MB size and are in dual-parallel/dual-stacked mode. ZynqMP: Fixed issue in booting Linux when Vivado project has isolation configuration enabled. Versal: Added PMC I2C DT nodes
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Device-tree Generation (DTG) | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Removed phy-type property as it was deprecated in 2022.1. Update phy-mode as usxgmii for usxgmii IP If ILA ip connected to axi_switch M_axis port then build is failing. The reason is DTG unable to handles when axi_switch has more than one connected ips. 2022.2 DTG handles if multiple IPs connects axi_switch also. Fixed the undefined variable usage in mipi_csi2_rx tcl file as it was giving crash by saying undefined variable.
In ethernet subsystem if we have multicores then ethernet probe failed due to id is coming as int instead of string, fixed this issue. To mixer ip ip input ips connected then only add dmas property in mixer node. Fixed syntax errors when there are multiple ethernet ips in present in the design. Enable edac drivers ddrmc nodes based on ECC status set to true. Enhanced vcap node when it is connected through axi_broadcaster.
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Linux Kernel and Drivers | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Enabled config CONFIG_IRQCHIP_XILINX_INTC_MODULE_SUPPORT_EXPERIMENTAL by default through xilinx_dfeconfig. usb:gadget:tcm: Fixes error handling for each commands request for memory allocation fpga: of-fpga-region: Fix issue with incorrect power state where PL was powered up prior to Linux. fpga: Fixes memory leak warnings that occurs when overlay removed.
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OpenAMP and Libmetal | Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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VCU (Video Codec Unit) / Multimedia | | Fix for memory leak issue that was observed with GStreamer based low-latency VCU pipelines Release reset for DP before accessing DP registers. Accessing the DP register without releasing the reset makes system hang.
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QEMU | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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Xen | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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Libdfx | Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
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BSP, Drivers and Libraries | MicroBlaze Zynq-7000 Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Versal
| Fixed issue in iomodule Tcl with SSIT devices. Fixed issue in xscugic driver due to which interrupts are not getting routed to A72-1. Fixed an issue in xintc driver that can occur for MicroBlaze processor, XIntc_DeviceInterruptHandler() was using Xil_ExceptionEnable() , Xil_ExceptionDisable()which enables/disables interrupts and exceptions for MB instead of just enabling/disabling interrupts. Fixed issue with xil_excpetion.h which causes interrupt issues when xil_exception.h is included in application source. usbpsu: Fixed issue with USB non-ep0 data transfer command handling in non interrupt context. ddrcpsu: Fixed an issue with ddrcpsu for specific HW designs where psu_ddr is mapped to MicroBlaze in PL, but ddrcpsu is not mapped to it. Updated cputcl to correct toolchain path for libraries of MB64 iic: Fixed read fail issue when byte count is one. xilffs: Fixed unaligned sector size read issue. Fixed ipipsu driver issue MB. Fixed MRMAC Linux driver link status detection as per IP recommendations to include block lock, alignment and hi-ber checks. In addition, addressed a corner case for 10G/25G where a false link up can be reported, by adding a check for recent RX valid code. Fixed EDAC DDRMC driver probe issue when more than one DDR is enabled in the design. Fixed suspend resume issue with OSPI boot. Fixed value of entropy size passed while collecting random data from entropy source in HRNG with DF mode (TRNGPSV driver) Enabled config CONFIG_IRQCHIP_XILINX_INTC_MODULE_SUPPORT_EXPERIMENTAL by default through xilinx_defconfig. usb:gadget:tcm: Fixed error handling for each commands request for memory allocation fpga: of-fpga-region: Fixed issue with incorrect power state when PL was powered up prior to Linux. fpga: Fixed memory leak warnings that occurs when overlay removed. xiic: Corrected the BNB interrupt enable sequence Fixed CAN errors with 1Mbps/5Mbps arbitration/data rates Fixed issue with CPU hot plug. During the USB gadget enumeration, unwanted spurious interrupts are triggering, which causes the false hibernation state and this is fixed now. Fixed QSPI Chip select timed out issue. crypto: Fixed the hang issue by returning error code if data size is out of bounds instead of hanging due to assert.
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XilSEM | Versal | Runtime checks if CRAM/NPI scan is enabled in the design Validation of user-specified NPI scan frequency (valid range: 80 to 1000ms) Removed PSM RAM dependency during descriptor processing Improve NPI scan error log Separate events for error notification Fixed CRAM scan clock divisor value as per CIPS settings Fixed GT memcel arbitration issue Optimization in polling loops, stack usage, redundant checks in NPI scan Source code readability improvement: doxygen conformance, remove todo comments
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Image Recovery (SOM Kria) | Zynq UltraScale+ MPSoC | Assorted fixes to Image recovery GUI. Update to flash erase mechanism to erase whole image area. Fix incorrect handling of PageSize for stacked mode.
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