2020.1 Release Notes for Open Source Components

Owned by Sandeep Gundlupet Raju (Unlicensed)
Last updated: Nov 24, 2020
6 min read

This page provides details on the 2020.1 release information such as new features and bug fixes for all the Xilinx Open Source Components. 

Table of Contents

New Features

Note:

  • Each "Component Name" has a link to respective pages. For more details refer individual pages.
  • Versal content is in bold font
Component Name
Platform/SoC Supported
Feature Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Upgrade Yocto Project version to 3.0 Zeus release
  • Vitis AI packagegroup including DNNDK ( For Zynq UltraScale+ MPSoC Only)
  • Boot image generation on target
  • OpenAMP, Xen Hypervisor support
  • Add additional host dependencies to buildtools-tarball
  • OCI container integration
  • Baremetal toolchains using Yocto Project sources
    • Used by Vitis in addition to the existing Linux toolchains

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC

  • Subsystem restart support - Added support for RPU only restart in Zynq UltraSacle+ MPSoC/RFSoC

PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • PMUFW optimization to reduce memory footprint
  • Add optional feature to trigger error if RPU is ever suspended or powered down at runtime
PLM (Platform Loader and Manager)
  • Versal
  • SSIT - Slave SLR configuration support
  • Secondary boot mode support (OSPI, QSPI, SD/eMMC/PCIe)
  • Boot time measurement support
  • Security features - Checksum, Authentication (SHA-RSA/ECDSA) and Decryption (AES) of partitions/images.
  • Error Management (Basic - Hardware Errors)
  • SEM integration 
  • IDCODE/Extended-IDCODE checks in PLM
  • Added support for OSPI DDR mode in PLM
  • Added support for PS reset from XSDB
  • Linux runtime power management support
  • AIE power and reset managed by PLM
  • Early PL housecleaning to shorten boot time by ~10msec
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Upgraded the ATF to V2.2 version
  • Added JTAG DCC support as per the new framework
  • Add missing pin control group for Ethernet 0 for Zynq UltraScale+ MPSoC/RFSoC
  • Added support for PLM to ATF handover
  • Use defaults when PDI is without SW partitions for Versal
U-Boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Upgraded U-Boot to mainline 2020.01 version
  • Added distro boot support for Zynq-7000, Zynq UltraScale+ MPSoC/RFSoC devices, For more details refer Using Distro Boot With Xilinx U-Boot
  • Added support for UBIFS file system for NAND Flash (with hw ecc and on-die ecc)
  • Added common defconfig (xiling_zynqmp_virt_defconfig) for all Zynq UltraScale+ MPSoC/RFSoC devices
  • Added common defconfig (xilinx_zynq_virt_defconfig) for all Zynq-7000 devices
  • Added distroboot support for Zynq-7000, Zynq UltraScale+ MPSoC/RFSoC devices
  • Added common defconfig (xilinx_versal_virt_defconfig) for all Versal devices
  • Added support for Watchdog driver
  • Added support for Secure Partial bitstream loading
  • Added support for Loading non-secure AIE Kernel
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Added MRMAC IP initial support
  • Removed the hardcoded video pipeline for multimedia IPs
  • Added DPU IP support
  • Replaced the hardcoded values with the macros for reset and power
  • Added DMA channels for axi_mcdma IP support
  • Added support to load encrypted bitstream using FPGA manager in kernel for Zynq-7000 
  • Generate the memory node for each axi_noc IP for Versal
Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Kernel upgrade to v5.4 version.
  • AXI I2C Driver Support for greater than 255 byte reads.
  • Added RTC calibration set/get offset support
  • Versal OSPI driver
    • Added support for file systems like UBIFS and JFFS2.
    • Added support for RX periodic tuning.
  • Added support for Clocking wizard driver
  • AXI UART Lite Support
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • MicroBlaze softcore in PL as remote - IPC w/o IPI (no lifecycle management support)
  • R5 as lifecycle management master to start APU remote (no IPC)
  • OpenAMP drivers upgraded for Linux 5.4 kernel
  • OpenAMP Versal drivers upgraded for Linux 5.4 kernel
VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC
  • Added support for HDR10 metadata insertion and extraction at VCU control software level
  • Enabled buffer metadata to indicate encoder frame-skip frame to application
  • Added custom ROI delta-qp (roi-by-value) support to encoder
  • Added support for external plug-in rate control support at OMX/GStreamer level
  • Enabled Audio with LLP2 support
  • GStreamer version upgraded to 1.16.1
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Support for PMU MIO pins through SystemC
  • Enhanced RTC Support for Zynq UltraScale+ MPSoC/RFSoC devices.
  • Support for key loading library via BBRAM and eFUSE keys for Zynq UltraScale+ MPSoC/RFSoC devices.
  • Enable Support for Basic Cryptographics Services for Zynq UltraScale+ MPSoC/RFSoC devices.
  • Supporting XMPU & XPPU for Versal.
  • Sharing DDR memory space between QEMU and Verilog/VHDL Vivado Simulation.
  • Enhanced RTC Support for Versal.
  • Support for AXI QSPI IP.
  • Support for key loading library via BBRAM and eFUSE keys for Versal.
  • Support for eFUSE programming and reading via Library for Versal.
  • Enable Support for Basic Cryptographics Services for Versal.
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Enable RunX Containers as VMs within Xen
  • Support for Cache Coloring for time sensitive systems in Xen
  • Released ImageBuilder for Xen Hypervisor  Dom0-Less usage
  • Support for PL Device Passthrough to DomU in Xen
  • Enable support for building Docker/OCI containers on Zynq UltraScale+ MPSoC/RFSoC devices
  • Enable Docker/OCI Containers running as VMs in Xen to access slave PL Resources
  • Enable support for building Docker/OCI containers on Versal devices
BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Xilfpga library

    • Adopted Bitstream Configuration and readback support using IPI mechanism for Zynq UltraScale+ MPSoC/RFSoC devices

    • Added eFuse checks in the bitstream validation path for Zynq UltraScale+ MPSoC/RFSoC devices

    • Add support for secure readback feature for Zynq UltraScale+ MPSoC/RFSoC devices

    • Added Partial PDI loading support for Versal devices
  • Added support to use PMU cycle counter for delay generations in Cortex-R5 if the design does not have TTC enabled
  • Added support of AXI PCIe3 in its tcl for generation of required parameters in xparameters.h 
  • Versal OSPI
    • Added non-blocking DMA read support.
    • Provided user API to perform RX periodic tuning.
  • Added support for Clocking wizard 
AI Engine(AIE)
  • Versal* (AI Core Series)
  • Error and Event Management for AIE
  • Out-of-box example with 400 AIE cores
  • FPGA Manager support for AIE

Bug Fixes

Note:

  • Each "Component Name" has a link to respective pages. For more details refer individual pages.
  • Versal content is in bold font
Component Name
Platform/SoC Supported
Bug Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fix U-Boot defconfig for kc705-microbalzeel machine configuration file
  • Fix incorrect SRC_URI for tcf-agent in meta-petalinux layer
  • Pull upstream patches to add support for alternative URL formats from git submodule files
  • Added Qtgraphicaleffects package to packagegroup-petalinux-qt-extended
  • Fix for PMUFW build overflow issue when you enable ENABLE_EFUSE_ACCESS PMUFW debug flag for Zynq UltraScale+ MPSoC devices.

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Added Address Mirroring enable support in DDR SPD for Zynq UltraScale+ MPSoC
  • Add Macronix 2G flash support in FSBL for Zynq UltraScale+ MPSoC
  • Fix Zynq UltraScale+ MPSoC Reset Validation functionality (XFsbl_ResetValidation) considering both WDT0 and WDT1
  • Add Macronix 1.8V 512MB flash support to Zynq-7000 FSBL
PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Provide option to disable FSBL copy to DDR for warm restart case
  • Idle and reset sequence fixes for NAND, GPU_PP, CAN, zDMA
  • GEM Idle sequence update
  • Updates to make sure RPUs are isolated before being reset
  • Fix to ensure RPU AMBA is reset during RPU power down
  • Multiple code optimizations to free up ~6KB of PMU RAM (thereby fixing issues related to footprint limitation)
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • PINCTRL_GRP_ETHERNET0_0 missing in static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN]
U-Boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Fix file access from U-Boot when formatted NAND flash with UBIFS in Zynq UltraScale+ MPSoC
  • Unable to load encrypted Linux image along with rootfs
  • PetaLinux unable to read MAC address from EEPROM
  • Pings on GEM Interface cause NFS to time out


Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • MicroBlaze reset using GPIO cannot be done from Linux
  • VPPS - DTG fails if AXIS Substset converter is connected to external interface
  • DTG doesn't generate "ports" node for HDMI Tx IP
  • Not supported pl_clk warnings
  • DTG error when generating ps_axi_lite node
  • PetaLinux fails to build device-tree using template flow
  • DTG error sw_vproc_ss::generate for design with multiple copies of image processing pipeline
  • Remove hardcoded DTG nodes for VCU multimedia pipelines
  • DTG for the audio formatter gives incorrect output if there is an ILA in the path
  • DTG generate nodes for VCU decoder when it is disabled from Vivado design


Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • QSPI flash with JFFS2 fails in Linux kernel when spi-tx-bus-width is set to 4
  • Fixed junk characters on serial port issue, by monitoring TACTIVE bit in cdns_uart_set_termios
  • Linux drivers printing misleading error messages when devm_clk_get() fails with EPROBE_DEFER
  • SD default to high speed mode
  • Fixed uartps cdns_uart_get_mctrl broken by setting RTS and DTR based on modem configuration
  • I2C mux(pca954x) channel configuration write always
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC

VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC 
  • Fixed gstreamer parser bugs which caused crashes with third party video files
  • Provided custom gstreamer application to improve quality when using GDR mode by modifying delta-qp, alpha, and beta offsets
  • Fixed coverity check errors in control software
  • Fixed target bitrate in interlaced mode
  • XAVC SEI message buffer size is increased to avoid video hang/corruption for AVC encoder.
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC

Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • EEMI Mediator fixes for Zynq UltraScale+ MPSoC/RFSoC devices, including TCM, PL, AIE, OCM and R5 access
  • EEMI Mediator fixes for Versal devices, including TCM, PL, AIE, OCM and R5 access
  • GIC v3 ISACTIVER emulation fix
  • Fixed reserved-memory mapping
  • Rebase on Xen 4.13 comes with upstream several fixes
BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC

  • Zynq UltraScale+ MPSoC XilFPGA: Fixed an issue where some of security checks were bypassed if user passes non secure flags.

    • Improved security handling in XilFPGA by fixing few identified potential security holes.

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