2021.1 Release Notes for Open Source Components

This page provides details on the 2021.1 release information such as new features and bug fixes for all the Xilinx Open Source Components. 

Table of Contents

New Features

Note:

  • Each "Component Name" has a link to respective pages. For more details refer individual pages.
Component Name
Platform/SoC Supported
Feature Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • If RSA_EN is not programmed and bh_auth is not enabled in bif, FSBL loads the bin as non-secure bin irrespective of whether the partitions are authenticated or not.
  • FSBL provides a user config: FSBL_PL_LOAD_FROM_OCM_EXCLUDE_VAL which is set to 1 by default. Setting this to 0 will ensure bitstream would be loaded in chunks from OCM even if DDR is present in design, in DDR less designs, bitstream is loaded from OCM irrespective of the flag.
PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • None
PLM (Platform Loader and Manager)
  • Versal
  • Functional Safety certification and FMEDA support (PLM and Sec libs)
  • Multiboot support at run-time
  • PLM Image Store updates at runtime
  • PLM Size improvements
  • CRC support for IPI in PLM & PSM
  • PLM_SECURE_EXCLUDE to exclude security code
  • PLM Access controls
  • Configuration of EM error actions using error mask instead of error ID.
  • Configuration of multiple errors of same error error at a time.
  • NOC clock gating when NOC is not in use
  • Linux kernel drivers to register and be notified of system errors
  • PSM watchdog/keeepalive check from PLM
  • Features available only in Decoupling workflow:
    • Device capabilities for secure, coherency, virtualization configurations
    • Healthy boot of subsystem
    • Default xPPU/xMPU protections for PMC/PSM
    • Subsystem permissions for access control to devices and other resources
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Added the error management support.
  • Added the missing IDs for ZynqMP.
  • Created a common macro for CRC checksum.
  • Mark IPI calls secure/non-secure.
  • Add support to reset SGI.
  • Added support for XCK26 silicon ID.
U-Boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Upgraded U-Boot to mainline 2021.01
  • zynqmp mmio_read and zynqmp mmio_write commands are available to access secure registers from U-Boot

  • Added Common Clock Framework(CCF) functionality to enable and disable clocks in U-Boot.
  • Added Block protection support for Micron SPI flash devices.
  • Added Support for storing ENV on media which is used for primary bootmode.
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Added the clock support for axis_switch IP.

  • ZOCL device tree support was added.
  • Cascade mode support for axi intc controllers.
  • For mipi_csi_rx IP the reset_gpios property was added.
  • For mipi_csi_rx IP added the compatible string for backward compatibility.
  • Removed pinctrl properties when IPs gpios are configured as EMIOs.
  • Updated the acpu frequency based on the design.
  • Added the clock wizard IP support for versal.
  • Updated the alias nodes with PS IPs as priority.
  • Removed the clock workaround clk_ignore_unused in DTG.
  • Generate the video_clk as per the design.
  • hdmi_tx: Add the vid-interface property.
Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Kernel upgrade to v5.10 version.
  • OSPI Macronix flash part support.
  • DDRC EDAC Linux driver support for Versal using Error Management
  • AXI I2C standard mode read support in Linux driver.
  • Added Linux GPIO driver for ZynqMP mode pins.
  • Added MRMAC one step PTP support and bugfixes for link initialization.
  • Added AXI Ethernet ethtool statistics reporting on AXIDMA and MCDMA..
  • Added support to load secure bitstream(more specifically a secure PDI that is encrypted with volatile user key).
  • Added support to ensure that existing AXI INTC driver (drivers/irqchip/irq-xilinx-intc.c) can operate as a module when loaded through a DT overlay.
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • No new features other than 2020.10 OpenAMP component upgrade
VCU (Video Codec Unit)
  • Zynq UltraScale+ MPSoC
  • Gstreamer version upgraded to 1.16.3
  • GRAY8/GRAY10 format support is added for VCU encoder/decoder at Gstreamer
  • Dynamic IDR insertion support is added for Pyramidal GOP
  • Added external CRTC (ex: PL video-mixer) support to PS-DP subsystem.
  • Uniform slicetype parameter support is added for VCU encoder
  • Vertical alignment/crop on input buffers is supported for VCU encoder
    • used in 486i to 480i conversion.
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Merge with QEMU 5.1 from mainline
  • Versal: WWDT support
  • Versal: Basic Sysmon support
  • Versal: XRAM and XRAM Controller support
  • Versal: PSM Halt support
  • Versal: CanFD fixes
  • Versal: Improve reset coverage
  • Versal: Add support for direct SMP Linux boots
  • ZU+: zynqmp: Add K26 SOM and Starter-kit virtual boards
  • ZU+: Fix a APU WFI propagation to PMU bug
  • MicroBlaze: Add TrustZone support
  • remote-port: ATS support
  • remote-port: Bus-access device error reporting
  • remote-port: Add an iomem-cache caching memories implemented in SystemC/RTL
  • eMMC Improvements
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Rebased on Xen 4.14
  • Xen support for dynamic discovery of new PL blocks at runtime
  • Assignment of discovered PL blocks to new Xen Virtual Machines
  • Cache Coloring PV drivers support
BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • XilSecure Client support is added for A72/R5 processors
  • Remaining eFuse read/write support 
  • Added Environmental monitoring support is XilNvm library before programming eFuses
  • eFuse read/write classification is added for IPI requests in XilSKey library for ZynqMp
  • User key decryption support is added and interface to load user keys is provided by PMC_DATA.CDO
  • Authentication of IHT as AAD
  • Clearing of PUF ID
  • Storing Secure State of Boot in RTCA for run time use
  • KAT for ECDSA P521 curve
  • Checks that encryption key source of metaheader is same as that of PLM
  • Authentication of PLM loadable partitions using ECDSA P521 curve for A-HWRoT boot mode
  • OSPI Macronix flash part support.
  • Added Flash read/write example for QSPI NAND device
  • Added example for SPI SLM9670 TPM device which can perform different tpm2 commands based on user options.
  • Added AXI Timer driver support for Versal platform.
  • Upgraded FreeRTOS to version 10.4.3.
  • Added support to load secure bitstream(more specifically a secure PDI that is encrypted with volatile user key).
  • Baremetal Dhrystone application present in embeddedsw sw_apps has been enhanced to add support for all Xilinx supported platforms/CPUs.
AI Engine(AIE)
  • Versal* (AI Core Series)
  • Batch processing ( Transaction Mode)
  • AIE resource Manager ( profiling resources)
  • Functional Abstraction Layer for AIE ( AIEFAL)
  • SYSFS for AIE errors and status dump
  • Driver support for Timer Sync

Bug Fixes

Note:

  • Each "Component Name" has a link to respective pages. For more details refer individual pages.
Component Name
Platform/SoC Supported
Bug Description
Yocto
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • To be updated

FS-Boot

Zynq-7000 FSBL

Zynq UltrsScale+ FSBL

  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Fix secure boot issue in USB boot mode
  • Resolved build issues in DDR less and SECURE_EXCLUDE cases
  • Avoided I2C writes to TCA6416A for ZCU208,216
    • Fix Wrong Address/Length in Initialization TCM ECC prints
  • Fix to enable RSA Authenticated images boot as non-secure when RSA_EN is not programmed

PMUFW (Platform Management Unit Firmware)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Error messages seen in kernel log "cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP for freq 1333333320 (-34)" if CPU frequency different from device tree operating points. Workaround here: https://www.xilinx.com/support/answers/71070.html
  • Fix reset ops for assert() calls
  • Fix voltage status param reading
PLM (Platform Loader and Manager)
  • Versal
  • PL/SOC power supplies ramp up time at POR is expected to be under 250usec. If customer board rail ramp-up is longer, this can cause PLM timeout. This will be fixed in future PLM using sysmon for Power good checks.
  • Fixed bug in XPlmi_DmaWriteKeyhole to support various keyhole sizes
  • Fix to correctly show the reset reason when EAM enabled and after SRST
  • Fixed PLM build issues in Yocto Project workflows
  • Fix maximum number of entries for ATF
Secure libraries and drivers
  • Versal
  • Zynq UltraScale+ MPSoC
  • XilSecure: Fix to make XSecure_MemCpy64 work with unalinged data
  • XilNvm: Disable BBRAM Programming mode in case of write key failure.
  • Fixed build issues for XilNVM, XilPUF examples with C++ compiler
  • XilSKey: Fixed bug related to Device ID detection
  • XilSKey: Fix to resolve issue with not allowing PPK hashes to be programmed more than once
  • Linux NVMEM driver: Fixed Issue in reading PPK0/1 hash
  • Linux SHA driver: Fixed hang issue by adding mutex
  • Linux RSA driver: Fix to enable the driver to use skcipher API instead of blkcipher
Arm Trusted Firmware (ATF)
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • ZynqMP: Fixed missing ids for 43/46/47dr devices. Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp devices.

  • dcc: Fixed the return type for console_flush function.

  • docs: Update the make command.


U-Boot
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Fixed loading application on R5 core1 from u-boot.
  • Fixed issue in SD and Ethernet when subsystem reboot is issued.
  • Fixed clock dump to show proper clock rates.
  • Fixed QSPI baud_rate value calculation when qspi reference clock is the 2^n multiple of the spi-max-frequency
  • Fixed AXI-QSPI driver which was not working properly.
  • Fixed Spansion qspi flash(s25fl256s) detection issue
Device-tree Generation (DTG)
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Fix the DMA channel interrupt issue.
  • mrmac: Remove the hardcoded base address for mrmac cores.

  • axi_dma: Update the datawidth for the S2MM interface

    When the interface is S2MM, use the config CONFIG.C_S_AXIS_S2MM_TDATA_WIDTH for the datawidth property.
    
  • axi_eth: Fix the xxv_ethernet multicore address issue .The designs can have enabled the multicores but the address for each core  might not present. In this case dont generate the other cores.

  • Fix the labels for the custom IPs for demosaic 
  • axi_ethernet: dclk wont be present in MAC only case. The 10G/25G ethernet subsystem is  configured as MAC only, then dclk wont be present.

  • common_proc: Fix the logic for remote endpoint mappings.

  • Fix the issue when mappings are not updated for the multimedia IPs.

  • axi_etherenet: Fix logic for phy-mode property. If the design has 1000BaseX the phy mode should be set to "sgmii".

Linux Kernel and Drivers
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Fixed MRMAC block lock polling mechanism and added clean exit for PTP TS FIFO timeout error (XXV and MRMAC).
  • Fixed error handling of Macb WOL-ARP when IP address is not set.
  • Updated Xilinx PCS PMA PHY driver to request reset after clock re-init.
  • Fixed QSPI flash write performance issue with tap delay configuration on every transfer.
  • Fixed USB3.0 RNDIS Gadget issue when MTU value is set to 15300.
  • Fixed Zynq-7000 RNDS ethernet gadget issue with iperf3 tool data rate drops to 0 bits/sec.
  • Fixed ZynqMP PS DDR EDAC driver reporting incorrect error count information.
  • Corrected RTC calibration value to 0x7FFF as per IP specification.
OpenAMP and Libmetal
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • A bus error caused by the new compiler on AArch64 Linux: rpc_demod: replace copy_from_shbuf w/.. metal_io_block_read
VCU (Video Codec Unit) / Multimedia 
  • Zynq UltraScale+ MPSoC 
  • Fixed V4l2 mem2mem driver reload/load issue.
  • Fixed gstreamer kmssink to display full screen mode for 4k wider monitors.
  • Fixed Xilinx dma driver to capture resolutions which are not aligned to 32, ex: 1400x1050.
  • Fixed overwriting SEI messages on BP and PT SEI messages.
  • Fixed kmssink to display planar 420 I420 video using PS_DP.
  • Fixed dppsu driver(baremetal) compilation with iar compiler
  • Hardcoding for NUM_INSTANCES in dppsu is removed.
QEMU
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Versal: CanFD fixes
  • Versal: Improve reset coverage
  • ZU+: Fix a APU WFI propagation to PMU bug
Xen
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Fixed handling of Set/Way cache maintainenance instructions when the SMMU is enabled
BSP, Drivers and Libraries
  • MicroBlaze
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Versal
  • Fixed VDMA interrupt example for optimization.
  • Common peripheral test fixes for new tool chain.
  • Fixed lwip DHCP timeout errors by updating Timer variable type.
  • Fixed ZynqMP DRAM test application eye test issue with different rank selection.
  • Fixed Zynq MP DRAM 2D Write Eye Test for DDR3-SDRAM device.
  • Added support for 16-bit bus width in ZynqMP DRAM test.
  • Fixed buffer overflow issue in Zynq and ZynqMp NAND driver with corrupted parameter page.
  • Fixed SPI multi byte transfer when FIFOs are disabled in the design.
  • Fixed XIicPs_MasterSendPolled hang issue when there is no slave device connected to master.
  • Fixed Zynq iicps transfer completion interrupt issue with improper hold bit handling.
  • Added sdps driver api for supporting non blocking write operation.
  • Fixed reading the CardId information and storing the Card Specific Data in the sdps driver structure.
  • Fixed Xilisf disk_status reentrant issue as API uses global variables.
  • Added helper function in uartlite driver to retain the status register information as status register is clear on read.
  • Fixed issue with microblaze build failure when DLMB/ILMB bram instances are present in the design.
  • Fixed issue with FreeRTOS bsp generation for MB when a TTC is mapped MB it but not connected as interrupt to it and instead an AXI timer is connected.

  • Fixed FreeRTOS - compilation fails if the -mxl-mode-bootstrap linker option is used.

  • Fixed cortex-A9 Xil_DCacheFlushRange with arm errata#588369 workaround.

  • Updated ZU+ xilfpga to load the authenticated bitstream image as non-secure image if RSA_EN is not programmed.

  • Update usleep() for better accuracy.

  • Updated cortex-A9 FreeRTOS exception handlers to capture required debug info.

  • Fixed issue of Standalone/FreeRTOS BSP generation failing for some Zynq MPSoC hardware designs where nFIQ is enabled.

  • Enabled configUSE_PORT_OPTIMISED_TASK_SELECTION for Microblaze FreeRTOS port.

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