RF Analyzer

RF analyzer is a dedicated debugging tool for the Zynq Ultrascale+ RFSOC family. This tool is board independent and can be used with custom boards as well as Xilinx development platform such as the ZCU208 or ZCU216. A JTAG interface is used to established communication between a host computer and a Zynq Ultrascale+ RFSOC containing an RF analyzer design. The user is allowed to generate a custom RF analyzer design containing the RFDC IP with specific settings or use pre-built RF analyzer bitstreams.

Table of Contents


In this wiki page, we cover the customization of the bitstream for use on custom boards as well as usage on the Xilinx evaluation boards, ZCU111, ZCU208 and ZCU216. The installation and general usage of the RF analyzer GUI is covered in UG1309.


Please refer to UG1309, ”Installing the RF Analyzer” section.

First time starting RF analyzer, Vivado path setup

RF analyzer requires the hardware sever as a minimum. The hardware server is installed by default with the Vivado lab edition, or Vivado System Edition.

The first time RF analyzer GUI is launched, the Vivado install path should be set:

This path is written into the RF_Analyzer.ini file present in the install directory, at the same level as the executable RF_Analyzer.exe.

Board detection and device configuration

Once the Vivado path is setup and the GUI starts, the “hardware target” tab opens. Hitting “connect” (#1 in the image below) will detect the JTAG cables, devices present in the JTAG chain, their status (configured/unconfigured), and if an RF analyzer compatible design is present. The results of this detection is displayed in the “Hardware” sub-window (#2 in the image below).

We can then select the part we want to configure in the “Hardware” sub-window (#2), select the bitstream (#3) and hit download bitstream (#4).

For this quickstart, we can use the pre-built bitstreams provided within the installation directory of RF analyzer. They are located in <RF_Analyzer Install directory>\Protocol\RFAnalyzer\bitstreams. To generate your own bitstream, please see the section below “Custom Bitstream Generation”.

Once the part is configured, we can select the Microblaze associated with the part and hit “Select Target” (#5). RF analyzer will read the RFDC IP configuration.

RF analyzer steps to download bitstream

Generation and Acquisition

When device configuration reading is complete, you will see a screen similar to the following:

Note that the external reference clocks should be present and their frequencies match the frequencies expected by the IP configuration. If not, the tiles might not be fully up and running.

To configure external clocks on the Xilinx evaluation board, please refer to “External Clock configuration on Xilinx evaluation boards” section of this wiki.

For Xilinx evaluation board setup, please refer to the relevant board section of this wiki.

The right-hand side of the window is used to display information about selected blocks, for example a single-click on “ADC Tile 0” will show:





DAC Signal Generation


  1. Double-click on DAC Tile 0.

  2. Double-click on DAC channel 0, (avoiding the selectable sub-blocks).



Click on "Generate" to start signal generation by the DAC.


ADC Signal Acquisition

  1. Double-click on ADC tile 0.

  2. Double-click on ADC 0, (avoiding the selectable sub-blocks).




Click “Acquire” to see the signal that has been looped back from DAC Tile 0: DAC 0. 

Select suitable windowing to reduce the distortion of the spectrum due to incoherence.





Custom Bitstream Generation

This section describes the steps required for customizing the Zynq UltraScale+ RFSoC RF Data Converter IP for a custom board and generating the bitstream of the IP example design. More detailed information for various RF Data Converter IP settings can be found in the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269).

Creating a Vivado Project

  1. Open the Vivado Design Suite.

  2. Click Create Project.


  3. Click Next.

  4. Enter project name and location.


  5. Click Next.

  6. Select RTL Project.


  7. Click Next.

  8. Use the filters to find your device.


  9. Select the device.

  10. Click Next and then Finish.

Adding and Customizing the RF Data Converter IP

  1. Click IP Catalog.


  2. Find the RF Data Converter IP (you can use the search field to search for it).

  3. Double-click the IP.

  4. Configure the IP as per your board requirement.


  5. Be aware of limitations (see Answer Record AR71746).

  6. To speed up the configuration, Predefined Configuration or Simple setup can be used.

Generating the RF Data Converter IP Example Design

  1. In the Advanced mode tab, enable the RF Analyzer.


  2. Click OK.

  3. You can skip the IP generation on the next screen.

  4. In the Source window, select the IP.


  5. Right-click and select Open IP Example Design.

  6. Select the path where the example project will be created.


  7. Click OK.

Generating the Bitstream

  1. The example project creates an IP integrator design.


  2. Note: You might have to zoom fit to see the full IP integrator design.

  3. Click Generate Bitstream.

  4. When generated, locate the bitstream at <example_design_path>\ip_name \ip_name.runs\impl_1.

  5. Use the instructions in UG1309 to drive the RF analyzer GUI.

External Clock configuration on Xilinx evaluation boards

External clocks delivered with the Xilinx Evaluation Boards can be programmed with the System Controller User Interface (SCUI) application.

  • For the ZCU1275, the SCUI can be found at:


  • For the ZCU111, the SCUI can be found at:

https://www.xilinx.com/products/boards-and-kits/ zcu111.html#documentation.

  • For ZCU216 (registration required):


  • For ZCU208 (registration required):


Alternatively, the RFDC Evaluation tool can also program the ZCU111, ZCU208 and ZCU216 clocks.

ZCU111 board setup

  • Connect the JTAG cable.

  • Connect DAC 229 Tile 1 Channel 3 to ADC 224 Tile 0 Channel 0

  • An optional filter can be used

  • Generate/Acquire waveforms as described in Generating a Signal and Acquiring a Signal from UG1309

  • With the this connection in place (as shown in the following image), DAC tile 1, channel 3 is connected to ADC tile 0, channel 0


ZCU1275 and ZCU1285 setup

  • Connect the bullseyes cable to the clock module output.

    • Bullseye 19/20 and 1/2 connect to ADC/DAC clocks

  • Connect the DAC/ADC bullseyes together through DC blocks.

  • Generate/Acquire waveforms as described in Generating a Signal and Acquiring a Signal from UG1309.

  • Connector 17/18 match DAC/ADC Tile 0 or 2, Channel 0

  • Connector 15/16 match DAC/ADC Tile 0 or 2, Channel 1


  • For more information, see:

https://www.xilinx.com/products/boards-and-kits/ zcu1275.html#overview

ZCU208 setup

The basic assembly from the RF DC Evaluation tool can be used: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/569017820/RF+DC+Evaluation+Tool+for+ZCU208+board+-+Quick+Start#Basic-Assembly


ZCU216 setup:

The basic assembly from the RF DC Evaluation tool can be used: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/246153525/RF+DC+Evaluation+Tool+for+ZCU216+board+-+Quick+start#Basic-Assembly

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