Fast RFDC DAC Shutdown with AXI traffic generator

In some application, it is necessary to quickly shut down the DAC output to prevent any spurious signals going into the downstream RF chain. For example, in case of a power supply failure, power supply instabilities can transfer to the downstream devices through the DAC and create spurious signals. These signals can potentially damage the downstream RF chain hence the necessity to quickly shutdown the DAC to prevent further failure.

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The design presented here is a light weight solution to shutdown the DAC tiles in a timely manner. It uses standard IP cores available in the Xilinx IP catalog: an AXI traffic generator in its simplest form, connected to an AXI interconnect. The AXI traffic generator writes to the necessary registers upon an external trigger. The external trigger is usually connected to the alarm of the central power supply unit (e.g. 12V main bus from where all other voltages derive). The AXI interconnect allows to set the highest priority on these register writes, ensuring the fastest shutdown possible. Since the solution is purely in HW, a very fast shutdown is achieved.

We also present a way of testing this design in this wiki. The target board used is the ZCU208, however, the solution is valid for all RFSOC Generation and DFE.

Base Design and its modification

The base design used is simply the RF analyzer design generated via the RFDC IP example design, targeting a ZCU208 (48DR). This will allow for a quick functional test since RF analyzer GUI is able to readback the tile status. It is also easily portable to a custom board.

The picture below shows the addition and connections for the modifications. The picture only shows the modified connections for ease of reading.

The AXI traffic generator (pink) and AXI interconnect (orange) are added to the design. The AXI interconnect is placed between the main control (blue) and the RFDC IP (orange). The clock and resets of the interconnect are all connected to the same clock as the smartconnect.

An external pin (red) is connected to the AXI traffic generator reset input, keeping it in reset until a failure is detected. In this case, to simulate a PSU failure, the external pin is connected to a DIP switch.

The target board is the ZCU208.


AXI traffic generator settings and initialization files

The AXI traffic generator is configured as in the picture below. The important settings are:

  1. Protocol “AXI4-Lite”, mode “system init”: these two settings allow to write a few registers when de-asserting the reset. The core is very light weight in this configuration.

  2. Ch-1 Base Address and High Address: These two addresses must correspond to the RFDC IP addresses. In this case, 0x44b00000 and 0x44b3ffff.

  3. Address and Data COE files: The two files initialize the small memory in the AXI traffic generator with the address and data to write. To shutdown one DAC tile, 0x3 must be written into the restart state register (offset 0x8) followed by 0x1 into the Restart Power-On State Machine Register (offset 0x4). Each tile address is offset at Tile_Id*0x4000 (refer to PG269, Ch. 4, Power-up Sequence → Power-Down Tile).


AXI interconnect settings

The AXI interconnect is setup with 2 slave (main control + AXI traffic generator) and one master (RFDC IP). The advanced configuration options box is ticked so we can set the slave priority.

The higher number will get the priority on the transaction, hence slave 01 is given a “1” priority.


Video of the modifications



After implementation, the RF analyzer GUI can be used to functionally test the design.

RF analyzer can read the tile status and the POR state machine state (picture below) when selecting a tile.

The trigger pin is connected to the DIP switch number 8 on the 208 board, circled in red in the picture below.

Once the tiles are up and running, we can toggle the dip switch to simulate a power failure, then refresh each tile status to check the tiles are in state 3.


RF analyzer is also able to restart the tiles by issuing a clock distribution command via the clock distribution screen.


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