This guide will walk you through the first steps of operating a ZCU670 Evaulation board. You will work with the contents of the kit itself as well as the RF Analyzer to setup the board.

Table of Contents

Introduction

The Zynq® UltraScale+™ RFSoC ZCU670 kit and RF Analyzer includes everything needed for quick out of box evaluation of the excellent DFE DAC/ADC performance. The RF Analyzer provides the perfect SW platform for easy generation and acquisition of RF signals to quickly get you moving toward the prototype/development stage.

To download the file go to the DFE lounge here: https://www.xilinx.com/member/rfsoc-dfe-documents.html. You must log into your Xilinx account and request access to get the file.

Board setup

Kit BOM

Open

Basic Assembly

1. Carefully attach the XM655 extender board with the screws provided.

2. Connect the power and network cables as shown.

3. Note the location of the Micro SD card slot.

4. Note the location of power switch.

5. Note the location of DIP switch SW2.

Open

XM655 connections

Example: Loopback between DAC Tile 0: DAC 0 and ADC tile 0: ADC 0.

1. Connect the HC2-to-SMA cables to locations JHC1 and JHC5 and tighten with the hex key provided.

2. Connect pins 0 and 1 of JHC1 and JHC5 to the 10MHz-to-1GHz baluns on the XM655 as show below.

3. Use the cable provided to interconnect J13 and J17 and complete the loop-back as shown.

Jumpers and Switch Settings

The ZCU670 will have all Jumpers and Switch Settings in their default position when unboxed.

1. Change DIP switch SW2 to SD boot mode as follows;

SD Card

1. Copy the files contained in folder <install_path>/image/670 onto a micro-SD card formatted to the FAT standard.

2. Insert the SD card into the ZCU670 SD slot.

Network connection

1. Connect a network cable between the board and host computer.

Power Up

1. Connect to a power source and turn on the board power using switch SW15.

2. The board powers on and boots from the SD card using the programmed images.

3. It takes approximately 60s for the operating system to fully boot and for the embedded software to start.

ZCU670 System Controller UI

This section describes the steps required for configuring the clocks on the RFSoC DFE ZCU670 Evaluation board using the Board System Controller User Interface

Starting the System Controller GUI

1. Open the RDF0629 – ZCU670 System Controller GUI (2021.1 ES) ZIP file

2. Extract these files to your C:\ drive

    

3. From C:\zcu670_scui, double click on BoardUI.exe

4. BoardUI will list the serial number if the USB cable is attached

5. The serial number is needed for this tutorial

6. Click OK

Setting the Si5381

1. Select the Set tab underneath the Clocks tab

2. Select Si5381A-zcu670_ZDM_HW_Test_01282021-Report.txt for the Design Report File

3. Select Si5381A-zcu670_ZDM_HW_Test_01282021-Registers.txt for the Register File

4. Click Set Si5381 Frequency button

   1. After completion, the frequencies are displayed

   2. These are based on the settings in the files, not an actual verification of the frequencies

       

Reading the Si5381

1. Select the Read tab underneath the Clocks tab

2. Click Last Set Si5381 Frequency button

   1. After completion, the frequencies are displayed

   2. Again, these are based on the settings in the files, not an actual verification of the frequencies

Si5381 clock files

These are the included Si5381 files

The Si5381 Readme PDF has more details on these clock files

Setting the clocks

1. Under the Set (Clocks) tab, make the following settings:

    

   1. Note: The PS frequency is 33 + 1/3

Reading the clocks

1. Select the Read tab

2. Click each of the Read buttons and verify the frequencies are set as shown

3. The PS frequency will only display 3 digits after the decimal point

Setting the 8a34001

1. Select the Set tab underneath the Clocks tab

2. Select 8A34001_BoardUI_test_1PPS.txt for the register file

3. Select 8A34001_BoardUI_test_1PPS.tcs for the tcs file

4. Click Set Si5381 Frequency button

Reading the 8a34001

1. Select the Read tab

2. Click Last Set 8a34001 Frequency button

   1. After completion, the frequencies are displayed

   2. These are based on the settings in the files, not an actual verification of the frequencies

8a34001 clock files

These are the included 8a34001 files

Setting Clock Boot Frequencies

1. Select the Set Boot Frequency tab

2. Type in your desired boot-up frequency and click the corresponding Set button

   1. IPI PS designs default to 33 + 1/3 MHz, so consider carefully changing the PSRefClk Boot Frequency; your PS design would need to be compiled with this new setting in mind

Restore Default Clock settings

1. Select the Restore Device Defaults tab

2. Restore the defaults by clicking the button associated with the clock you want to restore (300 MHz, 33.3333 MHz, and 156.25 MHz)

   1. These buttons make an immediate change to the frequency, if set differently

   2. These buttons remove any existing Set Boot Frequency setting, so at boot up, the default frequency is used

RF Analyzer

RF analyzer is a dedicated debugging tool for the Zynq Ultrascale+ RFSOC family. This tool is board independent and can be used with custom boards as well as Xilinx development platform such as the ZCU208, ZCU216, and ZCU670. A JTAG interface is used to established communication between a host computer and a Zynq Ultrascale+ RFSOC containing an RF analyzer design. The user is allowed to generate a custom RF analyzer design containing the RFDC IP with specific settings or use pre-built RF analyzer bitstreams.

Installation

Please refer to UG1309, ”Installing the RF Analyzer” section.

First time starting RF analyzer, Vivado path setup

RF analyzer requires the hardware sever as a minimum. The hardware server is installed by default with the Vivado lab edition, or Vivado System Edition.

The first time RF analyzer GUI is launched, the Vivado install path should be set:

This path is written into the RF_Analyzer.ini file present in the install directory, at the same level as the executable RF_Analyzer.exe.

Board detection and device configuration

Once the Vivado path is setup and the GUI starts, the “hardware target” tab opens. Hitting “connect” (#1 in the image below) will detect the JTAG cables, devices present in the JTAG chain, their status (configured/unconfigured), and if an RF analyzer compatible design is present. The results of this detection is displayed in the “Hardware” sub-window (#2 in the image below).

We can then select the part we want to configure in the “Hardware” sub-window (#2), select the bitstream (#3) and hit download bitstream (#4).

For this quickstart, we can use the pre-built bitstreams provided within the installation directory of RF analyzer. They are located in <RF_Analyzer Install directory>\Protocol\RFAnalyzer\bitstreams. To generate your own bitstream, please see the section below “Custom Bitstream Generation”.

Once the part is configured, we can select the Microblaze associated with the part and hit “Select Target” (#5). RF analyzer will read the RFDC IP configuration.

Generation and Acquisition

When device configuration reading is complete, you will see a screen similar to the following:

Note that the external reference clocks should be present and their frequencies match the frequencies expected by the IP configuration. If not, the tiles might not be fully up and running.

To configure external clocks on the Xilinx evaluation board, please refer to “External Clock configuration on Xilinx evaluation boards” section of this wiki.

For Xilinx evaluation board setup, please refer to the relevant board section of this wiki.

The right-hand side of the window is used to display information about selected blocks, for example a single-click on “ADC Tile 0” will show:

DAC Signal Generation

1. Double-click on DAC Tile 0.

2. Double-click on DAC channel 0, (avoiding the selectable sub-blocks).

Click on "Generate" to start signal generation by the DAC.

ADC Signal Acquisition

1. Double-click on ADC tile 0.

2. Double-click on ADC 0, (avoiding the selectable sub-blocks).

Click “Acquire” to see the signal that has been looped back from DAC Tile 0: DAC 0. 

Select suitable windowing to reduce the distortion of the spectrum due to incoherence.

Custom Bitstream Generation

This section describes the steps required for customizing the Zynq UltraScale+ RFSoC RF Data Converter IP for a custom board and generating the bitstream of the IP example design. More detailed information for various RF Data Converter IP settings can be found in the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269).

Creating a Vivado Project

1. Open the Vivado Design Suite.

2. Click Create Project.

    

3. Click Next.

4. Enter project name and location.

    

5. Click Next.

6. Select RTL Project.

    

7. Click Next.

8. Use the filters to find your device.

    

9. Select the device.

10. Click Next and then Finish.

Adding and Customizing the RF Data Converter IP

1. Click IP Catalog.

    

2. Find the RF Data Converter IP (you can use the search field to search for it).

3. Double-click the IP.

4. Configure the IP as per your board requirement.

    

5. Be aware of limitations (see Answer Record AR71746).

6. To speed up the configuration, Predefined Configuration or Simple setup can be used.

Generating the RF Data Converter IP Example Design

1. In the Advanced mode tab, enable the RF Analyzer.

    

2. Click OK.

3. You can skip the IP generation on the next screen.

4. In the Source window, select the IP.

    

5. Right-click and select Open IP Example Design.

6. Select the path where the example project will be created.

    

7. Click OK.

Generating the Bitstream

1. The example project creates an IP integrator design.

    

2. Note: You might have to zoom fit to see the full IP integrator design.

3. Click Generate Bitstream.

4. When generated, locate the bitstream at <example_design_path>\ip_name \ip_name.runs\impl_1.

5. Use the instructions in UG1309 to drive the RF analyzer GUI.

Next Steps

For more information on both silicon and boards refer to the RFSoC DFE lounge here: https://www.xilinx.com/member/rfsoc-dfe-documents.html