This page shows two specific examples of the RF DC Evaluation Tool to generate and acquire signals using the XM650 Add-on Card and the ZCU216 Evaluation Board.

Table of Contents

Introduction

The RF DC Evaluation Tool can be used to compare different scenarios and settings of the Zynq® UltraScale+™ RFSoC ADCs and DACs. In these two examples, we compare an direct sampling frequency versus the integrated RFSoC PLL.

Both examples use a Center Frequency (CF) generated from a DAC at 4700 MHz (N79 band F), loopback to the ADC through the XM650.

The only difference between these two example is the clock input to the RF ADCs and DACs:

• Example 1: Reference Clock provided via CLK104 via Samtec board-to-board connector

• Example 2: Direct Sampling clock via CLK104 SMP to SMP on ZCU216 base board. Requires SMP to SMP cables that are not included in the basic kit. More information about the cables and how to purchase them is located here: https://www.carlisleit.com/markets/test-measurement/customer-specific-products/xilinx/

Hardware setup

The hardware setup is shown in the picture below. Since the XM650 is a fully integrated loopback card, only the CLK104 cables need to be connected (for external clocking).

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To determine the sample rates, the RFSoC Gen3 Frequency Planning Tool was used. It is available at the link below:

• https://www.xilinx.com/publications/products/tools/zynq-ultrascale-plus-rfsoc-frequency-planner-rev1p7.xlsx.zip

ADC 2457.6MSPS CF=4700MHz w/100MHz BW

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DAC 9830.4MSPS CF=4700MHz w/100MHz BW

Example 1: Using the Reference Clock

In this example, we use one input reference clock for each ADC and DAC group, we distribute this reference clock to all tiles, and the PLL in each tile is used to multiply the distributed input clock and generate the sampling frequency.

For convenience and repeatability, we use a RF DC Evaluation feature which allows us to load a previously saved configuration, and previously saved waveform (preferences) file.

Load Configuration File for XM650 (n79) Loopback

To load the configuration file, go to the menu “File->load cfg file” and load the file below:

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Review Clock Settings

We can review the clock settings by clicking the “Clock Settings” button in the “Overview” tab:

Review Clock Distribution

We can review the clock distribution and sampling frequencies by clicking the “Clock Settings” button in the “Overview” tab:

Load Preference File for XM650 (n79) Loopback

To load the waveform file, go to the menu “File->load prf file” and load the file below:

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 This will open all necessary generation and acquisition windows to do a full 16x16 loopback, including the multiview DAC and ADC windows.

Generate DAC Tile[1:0] outputs (PEP = 0.0dBFS)

Using the first multiview DAC window, hit “Generate All” to generate all waveforms from this window:

Generate DAC Tile[2:3] outputs (PEP = 0.0dBFS)

Using the second multiview DAC window, hit “Generate All” to generate all waveforms from this window:

Acquisition of Tone Tile[1:0]

Similarly, use the first multiview ADC window to acquire all ADC from this window:

Acquisition of Tone Tile[3:2]

And the second multiview ADC window to acquire all ADC from this window:

 By clicking on the specific waveform, we can visualize the metrics for a specific ADC. Double clicking on a specific ADC will open the acquisition window for this ADC and give a more detailed view.

Example 2: Direct Sampling Clock

In this example, we modify the clock settings to compare metrics with the first example.

Clock Settings

The CLK-104 settings can be changed by clicking the “Clock Settings” button in the overview tab:

We can select the provided files to generate an external reference of 2457.6MHz for the ADC, and 9830.4MHz for the DAC.

Load Configuration File for XM650 (n79) Loopback

The configuration file for this example is provided below:

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Clock Distribution

The internal clock distribution settings by clicking the “Clock distribution” button in the overview tab. Note that all PLLs have been disabled, the reference clock for each tile and the input clock has changed from the first example:

Load Preference File for XM650 (n79) Loopback

The waveform file is provided below:

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Generate DAC Tile[1:0] outputs (PEP = 0.0dBFS)

The waveform files has populated the DAC multiview window with all DAC enabled and a single tone frequency of 4700MHz as shown below. Click “Generate All” to generate all the waveforms:

Generate DAC Tile[2:3] outputs (PEP = 0.0dBFS)

Again, click “Generate All” on the second multiview window to generate all the DAC waveforms:

Acquisition of Tone Tile[1:0]

The waveform files has also opened two ADC multiview window. Click acquire on these windows to capture the waveforms with the 16 ADCs:

Acquisition of Tone Tile[3:2]

Related Links

For more information on the ZU49DR silicon used on the ZCU216 board or the ZU48DR used on the ZCU208 board and any other RFSoC silicon visit https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html

For board schematics, BOM lists, user guides, and other documentation, go to the ZCU216 webpage located at https://www.xilinx.com/products/boards-and-kits/zcu216.html and the ZCU208 webpage located at https://www.xilinx.com/products/boards-and-kits/zcu208.html