This page shows two specific examples of the RF DC Evaluation Tool to generate and acquire signals using the XM655 Add-on Card and the ZCU216 Evaluation Board.

Table of Contents

Introduction

The RF DC Evaluation Tool can be used to compare different scenario and settings of the Zynq® UltraScale+™ RFSoC ADCs and DACs. In these two examples, we compare a direct sampling frequency versus the integrated RFSOC PLL.

Both examples use a Center Frequency (CF) generated from a DAC at 2150MHz, loopback to the ADC through a simple RF line up consisting of baluns and filters.

The only difference between these two example is the clock input to the RF ADCs and DACs:

• Example 1: Reference Clock provided via CLK104 via Samtec board-to-board connector

• Example 2: Direct Sampling clock via CLK104 SMP to SMP on ZCU216 base board. Requires SMP to SMP cables that are not included in the basic kit. More information about the cables and how to purchase them is located here: https://www.carlisleit.com/markets/test-measurement/customer-specific-products/xilinx/

Hardware setup

The hardware setup is described below and uses cable and filters provided with the ZCU216 Evaluation kit:

• ADC224_CH0 with DAC228_CH0 as source

• JHC1 DAC228 Channel 0 using 1-4GHz baluns

• JHC5 ADC224 Channel 0 using 1-4GHz baluns

• Connecting 10-2500MHz low pass filter for these experiments

• The picture below shows the board setup and connections

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Frequency planning

To determine the sample rates, the RFSoC Gen3 Frequency Planning Tool was used. It is available at the link below:

• https://www.xilinx.com/publications/products/tools/zynq-ultrascale-plus-rfsoc-frequency-planner-rev1p7.xlsx.zip

ADC 2457.6MSPS CF=2150MHz w/100MHz BW

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DAC 7864.32MSPS CF=2150MHz w/100MHz BW

Example 1: Using the Reference Clock

In this first example, the default settings of the RFSOC PLL, DAC and ADC are used except for the frequency generated.

Clock Settings

From the overview page, we access the CLK104 settings by clicking on “Clock settings”. For this example, only the REF Clock is important and is set to 245.76MHz (picture below).

The default setting is already at 245.76MHz, so no changes are necessary.

Clock Distribution

From the overview tab, by clicking on “Clock Distribution”, we can access the RFSoC internal clock settings. This tab controls the clock distribution, tile input clocks and sampling frequencies.

DAC228 (Tile0) Sampling Rate Details

The detail setup of a tile PLL can be visualized by clicking on the “PLL” in the specific tile:

DAC228 (Tile0, Ch0) Settings

The specific channel settings can be visualized by selecting a channel within a tile:

DAC228 (Tile0, Ch0) Muted Tone CF=2150MHz

In the DAC generation tab, we can change the Center Frequency to 2150MHz:

ADC224 (Tile0) Sampling Rate Details

Similarly to the DAC PLL settings, we can visualize the ADC PLL settings:

ADC224 (Tile0, Ch0) Settings

And similarly to the DAC channel settings, we can visualize the ADC channel settings:

 ADC224 (Tile0, Ch0) Acquisition of Tone

In the ADC acquisition tab, we can capture the signal and take measurements. Shown below are the dynamic performances over the full Nyquist zone:

ADC224 (Tile0, Ch0) Band of Interest (100MHz)

The band of interest around the fundamental can be narrowed down to obtain metrics more relevant to a specific application. The band of interest settings are available in the menu “settings->Dynamic performances”:

Example 2: Direct Sampling Clock

In this example, we modify the clock settings to compare metrics with the first example.

Clock Settings

Via the overview tab, we access the clock settings and select the ADC and DAC RFPLL according to our frequency plan (2457.6MHz and 7864.32MHz respectively):

Clock Distribution

In the clock distribution tab, we modify the ref clock for each tile, de-activate the PLL and change the tile clock source, as per the screen below:

DAC228 (Tile0) Sampling Rate Details

We can notice the changes in the PLL settings in each DAC tile:

DAC228 (Tile0, Ch0) Settings

All other DAC parameters are kept:

 DAC228 (Tile0, Ch0) Generate Tone with 0.0 PEP

We generate the same tone at 2150MHz:

ADC224 (Tile0) Sampling Rate Details

Again, we can visualize the ADC PLL settings:

ADC224 (Tile0, Ch0) Settings

And the ADC settings which are unchanged:

ADC224 (Tile0, Ch0) Acquisition of Tone

We can now acquire a tone and compare the metrics with the first example

ADC224 (Tile0, Ch0) Band of Interest (100MHz)

Reducing the band of interest show a very similar SNR between the two examples:

Related Links

For more information on the ZU49DR silicon used on the ZCU216 board or the ZU48DR used on the ZCU208 board and any other RFSoC silicon visit https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html

For board schematics, BOM lists, user guides, and other documentation, go to the ZCU216 webpage located at https://www.xilinx.com/products/boards-and-kits/zcu216.html and the ZCU208 webpage located at https://www.xilinx.com/products/boards-and-kits/zcu208.html