ZCU1275/ZCU1285 MTS Design Example

This page presents the MTS Design example for ZCU1275/ZCU1285 device.

Table of Contents

ZCU1275/ZCU1285 Build and Run Flow Tutorial

The below sections describe the build and run flow tutorial.

The design package for ZCU1275/ZCU1285 16X16 can be found at the following links:

Vivado Build Flow

Refer to the Vivado Design Suite User Guide: Using the Vivado IDEUG893, for setting up Vivado environment.

To build the hardware design, execute the following steps

On Windows

  1. Open a Vivado Tool.
  2. Navigate to the package folder path and change the directory to ../pl/MTS-IQ folder for MTS IQ design.
  3. On the Tcl Console of the tool, type

          source ./scripts/create_project.tcl

On Linux

Set $DCET_HOME environment variable as given below for linux environment.

  1. Open a Linux terminal.
  2. Change directory to $DCET_HOME/pl/MTS-IQ  folder for MTS IQ design.
  3. To create the Vivado IPI project and invoke the UI, run the following command.

After executing the script on windows/linux systems, the vivado IPI block design comes up as shown in the following figure.

4. Click the "Generate Bitstream" on left hand side of Vivado Project Panel.

The design is implemented, and a pop-up window comes up saying "Open Implemented Design". Click "OK".

Below figure depicts the view of opened implemented design.


5. Go to File > Export > Export Hardware

6. In the Export Hardware Platform for SDK window select "Include bitstream" and click "OK".

The HDF is created at $DCET_HOME/pl/MTS-IQ/project/zc1275_mts_design.sdk/zc1275_mts_design_wrapper.hdf for  MTS IQ Design.

PetaLinux build Flow

This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.

Refer to the PetaLinux Tool Documentation (UG1144) for installation.

  1. Sourcing petalinux tool.

      2. Post petalinux installation, $PETALINUX variable should be set, command to cross-check the variable.

      3. Create project from .bsp file

     4. Configure the PetaLinux project using step “a” or “b”.

         a) With the pre-built hdf located in folder ”pl/MTS-IQ/pre-built"  for IQ Design.

         b) If Vivado project is modified/design is changed, user is expected to configure the bsp with the modified .hdf file.

           For IQ

   5. Build all Linux image components along with Evaluation Tool application.

   6. Create a boot image (BOOT.BIN) including FSBL, ATF, PMUFW, bitstream and u-boot.

   7. Copy the BOOT.bin and image.ub to the sdcard.

Modifications on top of 2018.3 released BSP

Below are the modification in this TRD for linux-kernel, rftool and rftool-mts applications, on top of 2018.3 petalinux released BSP.

For more details on patch information please refer to http://xkb/pages/71/71829.aspx .The High level description is given below.

  • Kernel patch information
  • RFTOOL application patch
  • RFTOOL-MTS application patch

Modifications on top of 2019.1 released BSP

Below are the modification in this TRD for linux-kernel, rftool and rftool-mts applications, on top of 2019.1 petalinux released BSP.

For more details on patch information please refer to http://xkb/Pages/72/72417.aspx.The High level description is given below:

Kernel patch information

  • RFTOOL application patch
  • RFTOOL-MTS application patch


Modifications on top of 2020.1 released BSP

Below are the modification in this TRD for linux-kernel, rftool and rftool-mts applications, on top of 2020.1 petalinux released BSP.

For more details on patch information please refer to http://xkb/Pages/72/72417.aspx.The High level description is given below:

  • Kernel patch information
  • RFTOOL application patch
  • RFTOOL-MTS application patch
  • TRD Autostart patch information
  • RFDC Self-test application changes
  • RFDC Read-Write application changes
  • Device Tree Changes

The changes required with respect to pl memory nodes in kernel version 5.4 have been updated in the following path.

The changes required with respect to contiguous memory allocation (CMA size) are updated in the following path.

Modifications on top of 2021.1 released BSP

Below are the modification in this TRD for linux-kernel, rftool and rftool-mts applications, on top of 2021.1 petalinux released BSP.

For more details on patch information please refer to http://xkb/Pages/72/72417.aspx.The High level description is given below:

  • Kernel patch information
  • RFTOOL application patch
  • RFTOOL-MTS application patch
  • TRD Autostart patch information
  • RFDC Self-test application changes
  • RFDC Read-Write application changes
  • Device Tree Changes

The changes required with respect to pl memory nodes in kernel version 5.10 have been updated in the following path.

The changes required with respect to contiguous memory allocation (CMA size) are updated in the following path.

Run Flow

Clock Configuration for running the design



This Section Illustrates the steps to be followed for UART.

  1. To Configure RF PLL-A follow the steps described below to set 245.76 MHz clock.



2. To Configure FPGA REF_CLK follow the below steps to set 122.88 MHz clock.

(The default PLL clock frequency is 3072MHz and 3072/25=122.88 MHz.)

3. To configure Analog SYS_REF follow the steps described below to set 7.68 MHz clock.

(The default PLL clock frequency is 3072MHz and 3072/400=7.68 MHz.)

4. To configure PL_SYS_REF follow the steps described below to set 7.68 MHz clock.

(The default PLL clock frequency is 3072MHz and 3072/400=7.68 MHz.)

Clock Configuration Using System Controller User Interface (SCUI)

  1. The user needs to follow the below mentioned steps to program the clocks on hw-clk-103
    (a) Navigate to board UI folder in the SCUI package and open the board UI application.

               The user needs to enter the board information accordingly as shown in the figure below.


   (b) Go to File"change the system controller port". The system controller port window opens as shown in the figure below.

           c) On the windows machine,Go to Start→ Device Manager.

       In the system controller window choose the COM port corresponding to Silicon Labs Quad CP210x USB to UART Bridge: Interface 1.

     d) In the SCUI Go to CLK-103 section.

     e) The user needs to set FPGA REF_CLOCK ,SYS_REF and PL_SYS_REF.

     f) Choose the clock file "LMK04208_CKin112M8_3072MHz_HW_Test.txt" from the clockFiles folder in the SCUI package for LMK04208

         and enter the division factors for FPGA REF_CLOCK , SYS_REF and PL_SYS_REF.

         Enter the name of the clock file in the box provided,as shown in the figure below.

     Press "Set LMK04208 Frequency". Once the frequencies are set the log is as shown in the above figure.

   g) To configure "LMX2592_A" choose the clock file "LMX2592a_245.76MHz.txt" corresponding to 245.76MHz frequency

       from the clockFiles folder in the SCUI package.

       Enter the name of the file in the SCUI as shown below and press "Set LMX2592_A Frequency" .

       Once the frequencies are set the log is as shown in the below figure.

h) To configure "LMX2592_B" choose the clock file "LMX2592b_245.76MHz.txt" corresponding to 245.76MHz frequency

    from the clockFiles folder in the SCUI package. 

    Enter the name of the file in the SCUI as shown below and press "Set LMX2592_B Frequency".

    Once the frequencies are set the log is as shown in the below figure.

i) To configure "LMX2592_C" choose the clock file "LMX2592c_245.76MHz.txt"corresponding t o 245.76MHz frequency

   from the clockFiles folder in the SCUI package.  

   Enter the name of the file in the SCUI as shown below and press "Set LMX2592_C Frequency".

   Once the frequencies are set the log is as shown in the below figure.

Running the Test


  1. Once the targets boots, rftool application will be launched automatically.

   Refer to below screenshot for boot logs.

       2. From the shell prompt launch rftool-mts application by entering "rftool-mts"

       3. Once the rtool-mts application starts it prompts for options, select the options according to the use-case.

   Option 1 : To Generate and Acquire in mode 1

         After user selects option, a prompt will appear as shown below.

         Option 2: To Generate and Acquire in mode 2

        After user selects option, a prompt will appear to save ADC content to SD card.

        Press "Enter" to copy ADC data to SD card.

 

        Option 3: To exit the application

       After exiting the application ADC_DATA.csv file is copied in the SD card.

       Remove the SDcard and plot the ADC content in Excel sheet.

       Find below reference plot for IQ data capture. As can be seen in the plot all the signal sent through DACs and received through ADCs are aligned.

The below snapshot shows the code snippet to plot data in MATLAB using the .CSV file

IQ Data Capture (90 degree phase shift between I and Q components)