MTS Design

This section describes 16x16 (16-DAC, 16-ADC) channel MTS design. This example design is meant to demonstrate the Multi-Tile Sync (MTS) functionality of RFDC IP. 

Table of Contents

Clocking and Control 

This section focuses more on clocking aspects of this design. The features of various blocks are already covered in the top page.

The MTS design is clocked with PL clock as shown in the figure below. This PL Clock is derived from PL reference  clock listed as PL REF CLK (PCB) shown in figures below. The PL CLK is used for clocking AXI interface of both DAC and ADC channels.

Each DAC tile gets a dedicated clock from the  boards as shown in the figure as DAC # Analog Clock (PCB). Similarly each ADC tile gets a dedicated clock from the  boards as shown in the figure as ADC # Analog Clock (PCB). Apart from this RFDC block gets Analog SYSREF and PL SYSREF listed as SYSREF (PCB) and PL SYSREF respectively from the board that is required to enable Multi-Tile Synchronization.

User_sysref_dac and User_sysref_adc clocks are derived from PL REF CLK and sourced to DAC and ADC tiles respectively. These clock are used as reference for Multi-Tile Synchronization in tandem with Analog SYSREF and PL SYSREF clocks

For this design the table below has the details of clock frequencies selected for various clocks.

Sr No.

Clock Names

Clock Frequencies

Notes
1

DAC# Analog Clock (PCB)

245.76 MHz

Sampling rate selected is 3.93216 GSPS for xczu29dr and 4.42368 GSPS for xczu39dr

2

ADC# Analog Clock (PCB)

245.76 MHz

Sampling rate selected is 1.96608 GSPS for xczu29dr and 2.21184 GSPS for xczu39dr

3

PL REF CLK (PCB)

122.88 MHz


4

SYSREF (PCB)

7.68 MHz


5

PL SYSREF (PCB)

7.68 MHz



DAC Clocking

ADC Clocking

There is a common trigger signal for all channels so that all 16-channels are triggered as the same instant. These triggers are enabled by using channel control GPIO pins. As can be seen in figures above the common trigger from GPIO is synchronized in to DAC and ADC clock domains before being applied to fabric design.

RFSoC RFdc Build and Run Flow Tutorial

The following link will navigate the user to the RFSoC RFdc Build and Run Flow page for further details.

GPIO List

Function GPIO#FunctionGPIO#
Memory Loopback Reset0Reserved51
Reserved1Reserved52
DAC/ADC 16_Channel Control2Reserved53
DAC Loopback select3Reserved54
Reserved4Reserved55
Reserved5Reserved56
Reserved6Reserved57
Reserved7Reserved58
Reserved8Reserved59
Reserved9Reserved60
Reserved10Reserved61
Reserved11Reserved62
Reserved12Reserved63
Reserved13DAC Channel Mux Select64
Reserved14DAC Channel Mux Select65
Reserved15DAC Channel Mux Select66
Reserved16DAC Channel Mux Select67
Reserved17Reserved68
Reserved18Reserved69
Reserved19Reserved70
Reserved20Reserved71
Reserved21Reserved72
Reserved22Reserved73
Reserved23Reserved74
Reserved24Reserved75
Reserved25Reserved76
Reserved26Mode_Control77
Reserved27Reserved78
Reserved28Reserved79
Reserved29ADC Channel Mux select80
Reserved30ADC Channel Mux select81
Reserved31ADC Channel Mux select82
Reserved32ADC Channel Mux select83
Reserved33Reserved84
Reserved34Reserved85
Reserved35Reserved86
Reserved36Reserved87
Reserved37Reserved88
Reserved38Reserved89
Reserved39Reserved90
ADC_FIFO Reset40Reserved91
Reserved41Reserved92
Reserved42Reserved93
Reserved43Reserved94
Reserved44

Reserved45

Reserved46

Reserved47

Reserved48

Reserved49

Reserved50