This section describes 16x16 (16-DAC, 16-ADC) channel MTS design. This example design is meant to demonstrate the Multi-Tile Sync (MTS) functionality of RFDC IP. 

Table of Contents

Clocking and Control 

This section focuses more on clocking aspects of this design. The features of various blocks are already covered in the top page.

The MTS design is clocked with PL clock as shown in the figure below. This PL Clock is derived from PL reference  clock listed as PL REF CLK (PCB) shown in figures below. The PL CLK is used for clocking AXI interface of both DAC and ADC channels.

Each DAC tile gets a dedicated clock from the  boards as shown in the figure as DAC # Analog Clock (PCB). Similarly each ADC tile gets a dedicated clock from the  boards as shown in the figure as ADC # Analog Clock (PCB). Apart from this RFDC block gets Analog SYSREF and PL SYSREF listed as SYSREF (PCB) and PL SYSREF respectively from the board that is required to enable Multi-Tile Synchronization.

User_sysref_dac and User_sysref_adc clocks are derived from PL REF CLK and sourced to DAC and ADC tiles respectively. These clock are used as reference for Multi-Tile Synchronization in tandem with Analog SYSREF and PL SYSREF clocks

For this design the table below has the details of clock frequencies selected for various clocks.

DAC Clocking

ADC Clocking

There is a common trigger signal for all channels so that all 16-channels are triggered as the same instant. These triggers are enabled by using channel control GPIO pins. As can be seen in figures above the common trigger from GPIO is synchronized in to DAC and ADC clock domains before being applied to fabric design.

RFSoC RFdc Build and Run Flow Tutorial

The following link will navigate the user to the RFSoC RFdc Build and Run Flow page for further details.

GPIO List