Versal Platform Loader and Manager

This page provides information related to the Versal Platform Loader and Manager (PLM). 

Table of Contents

PLM Overview

The Platform Management Controller (PMC) in Versal has two Platform Processing Units (PPUs) to run Boot ROM and PLM respectively. PLM runs on the PPU Microblaze in PMC. PPU has 384 KB of PPU RAM and 128 KB of PMC RAM. PLM is responsible for doing the system initialization, booting and configuration of various devices as a part of Loader. It also takes care of secure boot which are authentication and/or decryption. After the initial boot is complete, PLM is responsible for Error Management, Partial Reconfiguration, Subsystem Shutdown/Restart, Health Monitoring and Soft Error Mitigation and remains active throughout the lifetime of the system.

During the initial boot, the Boot ROM decodes the Programmable Device Image (PDI) and loads the PLM into the PPU RAM. Once the PLM starts running, it will decode and process the rest of the PDI and boot up the system by loading the partitions present in the PDI. PLM also supports loading of the partial PDIs during run time.

Configuration Data Object

Configuration Data Object (CDO) contains set of commands which are required for configuring various components in the system. Any system configuration in Versal will come in the form of a CDO to PLM. These files are generated by the tools and are input to PLM. The CDO commands are registered by each module during module initialization phase. PLM decodes and passes this information to various modules for configuration. PLM copies the CDOs to PMC RAM in 64K chunks, decodes and processes them.

Please refer to UG1283 for PDI Specification

Modules in PLM

The PLM is designed with a modular subsystem-based configuration, and task-based services. Each functionally distinct feature is designed as a module. The PLM application layer contains the module initialization and start-up tasks. Depending on the modules selected in the configuration, different modules are initialized. Modules can register event handlers, IPI handlers, CDO commands, and scheduler events with the PLM interface layer.

Following are the list of modules present in the PLM:

  1. XilPLMI

  2. XilLoader

  3. XilPM

  4. XilSecure

  5. XilSEM

Note: XilLoader internally uses XilPDI library for loading the PDI image. Currently, XilPLMI, XilLoader and XilPDI are intended as PLM internal only libraries. Thus, APIs from these libraries are not intended to be called directly from other software layers outside of PLM.

Building PLM

PLM can be built using Vitis and XSCT. PetaLinux uses XSCT flow to generate PLM elf while generating PetaLinux project. Please refer to <tbd page> for PetaLinux flow. Also, Vivado generates a pre-built PLM with plm.elf name.

Using Vitis

Following are the steps to generate PLM elf using Vitis tool. Additionally, please refer to UG1305 to build PLM application

  1. Open Vitis

  2. Create new application project with File → New → Application Project…

    1. New Application Window will pop up as shown below.

    2. Click on “Next”. Select “Create a new platform from hardware (XSA)”, provide XSA File in “Platform” window and click on “Next”.

    3. In “Application Project Details”, Select psv_pmc_0 processor and enter “Application project name” as “plm”.

    4. Click on Next.

    5. Select “versal PLM” in Templates window and click on “Finish”.

  3. This would create PLM application with “plm_system” name along with the BSP.

  4. Right-click on “plm_system” folder and click on “Build Project” to build PLM and generate elf.

Using XSCT

Following are the steps to generate PLM elf using XSCT:

mkdir plm_ws cd plm_ws setws . app create -name plm -hw design.xsa -template "versal PLM" -os standalone -proc psv_pmc_0 app build -name plm

These steps will create and build PLM. PLM elf can be found at plm/Debug/plm.elf

Generating Boot Image

Boot image can be generated using BootGen command. We need to create a BIF file to generate Boot image. Also, please refer to UG1283 for more details on this.

  1. We already have PLM elf with us. Check the previous section to build PLM.

  2. Create and build PSM Firmware elf for PSM Microblaze.

  3. Create required applications for A72/R5, AIE, CPM etc.

  4. Create BIF file (boot.bif) with the below format

    all: { id_code = 0x14ca8093 //Add ID_CODE as per the Hardware extended_id_code = 0x01 id = 0x2 image { name = pmc_subsys, id = 0x1c000001 {type = bootloader, file = ./plm.elf} {type = pmcdata, load = 0xf2000000, file = ./pmc_data.cdo} } image { id = 0x4210002, name = lpd {type = cdo, file = ./lpd_data.cdo} {core = psm, file = ./psm_fw.elf } } image { id = 0x18700000, name = pl_cfi {type = cdo,file = ./design.rcdo} {type = cdo,file = ./design.rnpi} } image { id = 0x420c003, name = fpd {type = cdo, file = ./fpd_data.cdo} } image { id = 0x4218007, name = cpm { type = cdo, file = ./cpm_data.cdo} } image { id = 0x1c000000, name = def_subsystem { load = 0x1000, file = ./system.dtb} { load = 0x10000000, file = ./image.ub} { core = a72-0,exception_level=el-3, trustzone, file = ./bl31.elf} { core = a72-0,exception_level=el-2, file = ./u-boot.elf} { load = 0x4000000, file = ./rootfs.cpio.gz.u-boot} } image { id = 0x1c000000, name = def_subsystem { core = r5-lockstep, file = ./rpu_hello.elf} } }

     

  5. Below is the BootGen command to generate Boot image with the above boot.bif file.

    bootgen -arch versal -image boot.bif -w -o BOOT.BIN

Boot Modes

Following are the boot modes supported in Versal:

  1. SD/eMMC

  2. QSPI

  3. OSPI

  4. Slave device boot modes

    1. JTAG

    2. Select MAP

  5. USB (Only supported as secondary boot device)

  6. PCIe (Only supported as secondary boot device)

For more information, please refer to UG1304

Loading Boot Image on Hardware

We have created BOOT.BIN in “Generating Boot Image” section above. This image can be used to boot the Versal Hardware in any boot mode mentioned in “Boot Modes” section. In this section, we will see the steps to boot Versal in JTAG and SD boot mode.

In JTAG Boot Mode

Following are the steps to boot Versal Hardware in JTAG boot mode:

  1. Set the boot mode pins to JTAG on Hardware, power on and connect to board.

  2. Launch xsdb and connect to Hardware.

  3. Once the Hardware is connected, you will see the following targets when “ta” command is issued on xsdb terminal.

  4. Issue the following command to program the Hardware in JTAG boot mode.

  5. Once the Hardware is booted, PLM, PSM and the other application prints will come on the console in the sequence of the images mentioned in BIF file.

  6. Please refer to Debugging Tips section for more details on how to read PLM memory log and other debug tips.

In QSPI Boot Mode

Following are the steps to boot Versal Hardware in QSPI boot mode. Please refer to UG908 for more details.

  1. Initially, boot Versal in JTAG boot mode till U-Boot.

  2. Execute the following command in U-Boot on serial console to probe the flash device

  3. On xsdb terminal, execute the following commands to write QSPI boot image to DDR

  4. Then on serial console, execute the following commands in U-Boot to erase the flash memory and write the boot image to QSPI Flash

  5. Change the boot mode to QSPI and boot. It will boot the Versal Hardware in QSPI boot mode and loads the boot image that we have written to QSPI flash using the above mentioned steps.

In OSPI Boot Mode

Following are the steps to boot Versal Hardware in OSPI boot mode. Please refer to UG908 for more details.

  1. Initially, boot Versal in JTAG boot mode till U-Boot.

  2. Execute the following command in U-Boot on serial console to probe the flash device

  3. On xsdb terminal, execute the following commands to write OSPI boot image to DDR

  4. Then on serial console, execute the following commands in U-Boot to erase the flash memory and write the boot image to OSPI Flash

  5. Change the boot mode to OSPI and boot. It will boot the Versal Hardware in OSPI boot mode and loads the boot image that we have written to OSPI flash using the above mentioned steps.

In SD0/SD1/eMMC Boot Mode

Following are the steps to boot Versal Hardware in SD0 boot mode. Please refer to UG908 for more details.

  1. Initially, boot Versal in JTAG boot mode till U-Boot.

  2. Execute the following command in U-Boot on serial console to probe the emmc device

  3. On xsdb terminal, execute the following commands to write the boot image to DDR

  4. Then on serial console, execute the following commands in U-Boot to write the boot image to eMMC device

  5. Change the boot mode to SD0_LS/SD1_LS/SD1/eMMC and boot. It will boot the Versal Hardware in SD/eMMC boot mode and loads the boot image that we have written to SD/eMMC flash device using the above mentioned steps.

Note: The boot image can be directly copied to SD card and boot as well.

Secondary Boot

Any of the boot devices supported for secondary boot mode can be used as secondary boot device. Please refer to UG1283 for more details on secondary boot. Following are the steps for secondary boot process:

  1. PLM elf, LPD, Topology and PMC CDO and PSM elf must be part of primary boot image and any other images can be part secondary boot image.

  2. Specify the secondary boot device in the bif file. For example, if QSPI is chosen as secondary boot device and the secondary boot image stored at 0xC000000 location in QSPI, specify the same in primary boot image bif file before providing any image. Example bif file for primary boot PDI:

     

  3. When boot_device parameter is found in bif, BootGen will place the secondary boot device and secondary boot image details in image header table in meta header.

  4. When PLM sees this information, it will initialize the secondary boot device if it is other than primary boot device and will read the specified location and loads the secondary boot image.

  5. Example bif file for secondary boot PDI is below. Secondary boot PDI need to be generated and need to be copied to the boot device location as mentioned in the primary boot bif file. In this case, secondary boot image need to be copied to 0xC000000 location in QSPI Flash.

PLMI

The PLM Interface (XilPLMI) is a low-level interface layer for the PLM main application and other PLM modules. XilPLMI provides the common functionality required for the modules that run with PLM. Each new module can register itself with the supported command handlers which are executed based on the request received from other modules or from other subsystems. For more details on PLM modules, please refer to UG1304.

The XilPLMI layer provides the following functionalities:

  • Interface for parsing CDO commands and execution of the corresponding CDO command handler of any module.

  • Implementation for general PLM CDO commands

  • Interface for registering handlers for commands that can be part of CDO/IPI

  • Interface for scheduler timer events

  • Debug print levels and common utilities

  • Task Dispatcher

  • Interface to set error actions and register notifications for error events

  • Framework to update the PLM health periodically

  • Logging PLM terminal prints and the image trace log to the memory

Please refer to CDO spec for the list of CDO/IPI commands supported by XilPLMI.

IPI Handling

IPI is a key interface between PLM and other processor entities on Versal. PMC has a dedicated IPI channel assigned to it. PLM uses this IPI channel and its associated buffers for communication, which is initiated by other masters on Versal to PLM.

Data that is sent through IPI follows the same format of CDO. PLM uses IPI driver to send and receive IPI messages. PLMI implements IPI manager layer over the driver and it takes care of dispatching the IPI messages to the registered modules based on Handler and API ID in the IPI header.

PLMI implements IPI APIs provided for other Modules to perform the following actions:

  • Initializing and enabling IPI interrupts

  • Send IPI Message/response to a processor

  • Receive IPI Message/response to a processor

  • Dispatch received IPI message to corresponding registered module

Note: CRC can be enabled for IPI messages by setting ENABLE_IPI_CRC_VAL to 1U in xipisu.h file. This will add CRC validation check for IPI to/from communication. Please note that this setting need to be done in all application libraries for the Versal boot and post boot to work without any issues.

Task Modeling in PLM

PLM provides a very simple run-to-completion time-limited priority task loop model to get real-time behavior. This means that the main program is a simple loop that looks up the next task (typically a pointer to a function to be executed with a corresponding context data structure) from a queue of tasks and calls the function (executes the task) with the context as a parameter. Any interrupt that occur while the task is running, will obviously interrupt the execution, but since you are only allowed to do extremely simple things at interrupt level (i.e., disable interrupt and add a new task to the task queue), the task is logically executed in one chunk.

The complexity with the run-to-completion model comes when a particular task needs to run longer. If that happens, the task needs to be split into multiple events. There are three priority task queues, with Critical, High and Normal priority, Task dispatcher will check the priority queues in order and execute the Critical priority task handlers first. After executing task handler, dispatcher will check the task queues again and execute the next handler. If there are multiple tasks present in same queue, tasks will be executed one by one. All the tasks run to completion till task handler returns (i.e., there is no preemption). With no preemption, there will not be any need for locks and synchronization issues. Once the task is completed, it will be removed from the queue.

The priority order of the tasks are as below:

  1. Critical priority tasks (XPLM_TASK_PRIORITY_CRITICAL)

  2. High Priority tasks (XPLM_TASK_PRIORITY_0)

  3. Normal Priority tasks (XPLM_TASK_PRIORITY_1)

The general specifications for each PLM module are

  1. Run nothing in interrupt context; instead, add the necessary priority task to the task queue.

  2. To allow PLM to move on to the next high-priority task, the running task must not take longer time.

  3. No task should obstruct resources such as DMAs or CFI for longer duration.

Since PLM supports three priority tasks (Critical, High and Normal priority), below example shows how the user can create a high priority task within PLM

In the above example code, XPLM_TASK_PRIORITY_0 is passed to the XPlmi_TaskCreate function along with the task handler to create a task with high priority. Similarly, If user wants to create a Normal priority task, XPLM_TASK_PRIORITY_1 needs to be passed as priority argument for XPlmi_TaskCreate function.

Scheduler

Scheduler is a simple timer-based functionality to support execution of periodic/non-periodic tasks. A scheduler is required by modules such as XilSEM to support periodic tasks such as SEU detection scan operations. Scheduler also supports Critical, High and Normal priority tasks. The Critical priority tasks are given priority over High and Normal priority tasks.

Adding a task to scheduler

Tasks are functions which take void args and return the state of the task handler. Currently, PLM has no way to check that the task returns in a pre-determined time, so this needs to be ensured by the task design. Let us consider a task which prints out a message:

If we want to schedule the above task to occur every 100ms with highest priority, the following code can be used:

Removing a task from Scheduler

If we want to remove the previously scheduled task from the scheduler task list, the following code can be used:

Image Store

The Image Store feature allows PDI files to be stored in memory (DDR) and later be used to load specified images within the PDI. This is intended to allow partial reconfiguration, subsystem restart, etc without depending on external boot devices.
Also, this Image Store can be used as the Secondary Boot Device to use the PDI’s saved in the DDR.

PLM will have access to a dedicated DDR Location for storing of these user requested PDI's, the allocated DDR location address and size is Populated in the pre-defined RTCA region space for PLM to get the Image Store config details.

Currently user need to add below config at the end of “pmc_data.cdo” file before building the Boot PDI.

write 0xF2014288 <High 32bit addr> #Image Store Address High 32bit
write 0xF201428C <Low 32bit addr #Image Store Address Lower 32bit
write 0xF2014290 <Allocate size> #Image Store Allocated Size

*This above size which we give here is basically the total Image store memory allocated where multiple PDI’s are stored once the PDI add request is made.
Eg:

A new <PDI ID> field is added to the Add & Remove Image Store IPI command

Command: Add PDI to ImageStore

Reserved[31:25]=0

Security Flag[24]

Length[23:16]=4

XilLoader=7

CMD_ADD_IMG_STORE_PDI=9

PDI ID

High PDI Address

Low PDI Address

PDI Size ( In Words )

This command adds PDI address to the list of Image Store PDIs that are maintained by PLM. During restore or reload of a image, PLM checks this dynamically added list of PDIs first to get the required image and in case of any failure, it falls back to next possible. If no valid entry is present, it uses boot pdi, which is the first entry in the list. 

Response: Add PDI to ImageStore

Status (XST_SUCCESS / XLOADER_ERR_PDI_IMG_STORE_CFG_NOT_SET / XLOADER_ERR_PDI_IMG_STORE_FULL)

 

Command: Remove PDI from ImageStore

Reserved[31:25]=0

Security Flag[24]

Length[23:16]=1

XilLoader=7

CMD_REMOVE_IMG_STORE_PDI=10

 PDI ID

This command removes PDI address from the list of Image Store PDIs that are maintained by PLM.

Response: Remove PDI from ImageStore

Status ( XST_SUCCESS / XLOADER_ERR_PDI_ADDR_NOT_FOUND)

Also we can add the PDI via Boot Bif which will be part of CDO command (write image store) , in example below 2 pdi's will be added as a part of Image Store, 

Bif Example format below

write_image_store_pdi_1:
{
id_code = 0x14ca8093
extended_id_code = 0x01
id = 0x1
image
{
name = subsystem
id = 0x1c000008
partition
{
id = 0x9
core = a78-0
file = a78_0_ddr.elf
}
}
}

new_bif: {

id_code = 0x14ca8093
extended_id_code = 0x01
id = 0x1

image
{
name = pmc_subsys
id = 0x1c000001
partition
{
id = 0x2
type = bootloader
file = ./plm.elf
}
partition
{
id = 0x3
type = pmcdata,load=0xF2000000
file = ./pmc_data.cdo
}
}

image

{

  name = IMAGE_STORE

  id = 0x18700000

  partition

  {

   id = 0xb15

   imagestore = <Pdi id>

   section = write_image_store_pdi_1

  }

  partition

  {

   id = 0xb15

   imagestore = <Pdi id>

   file = partial.bin

  }

}

}

Image Store can also be used the Secondary Boot Device , as shown below via Boot Bif.

 boot_device { imagestore, address = <Pdi id> }

e.g : Secondary Boot from Image Store

As show below PLM will process the PDI and add the Images with PDI ID 10,12 to the Image Store and after that will check if any Secondary Boot Mode is specified and sees source is Image Store with PDI ID 12,

it then starts processing the partial PDI from Image Store.

new_bif: {

id_code = 0x14ca8093
extended_id_code = 0x01
id = 0x1

boot_device { imagestore, address = 12 }

image
{
name = pmc_subsys
id = 0x1c000001
partition
{
id = 0x2
type = bootloader
file = ./plm.elf
}
partition
{
id = 0x3
type = pmcdata,load=0xF2000000
file = ./pmc_data.cdo
}
}

image

{

  name = IMAGE_STORE

  id = 0x18700000

  partition

  {

   id = 0xb15

   imagestore = 10

   section = partial2.bin

  }

  partition

  {

   id = 0xb15

   imagestore = 12

   file = partial.bin

  }

}

}

Load Partial PDI is extended to support loading via Image Store

Command: LoadPartialPdi

Reserved[31:25]=0

Security Flag[24]

Length[23:16]=3

XilLoader=7

CMD_XILLOADER_LOAD_PPDI = 1

PdiSrc – 0x1 for QSPI24, 0x2 for QSPI32, 0x8 for OSPI, 0xF for DDR, 0x10 for Image Store

High PDI Address / 0x00 ( If PdiSrc Image Store )

Low PDI Address / PDI ID ( If PdiSrc Image Store )

Response: Load Partial PDI

Status (XST_SUCCESS / XLOADER_ERR_PDI_ADDR_NOT_FOUND)

Examples :

Following examples are present in the Xilloader Library.

Add PDI to Image Store : xilloader_add_image_store_pdi_example.c
Load PDI from Image Store : xilloader_load_pdi_example.c

Error Handling in PLM

Error Management HW

The Versal device has a dedicated error handler in PMC and PSM to aggregate all the fatal errors across the SoC and handle them. Refer to the TRM/Arch Spec for details. All fatal errors routed to PMC/PSM Error Manager can either set to be handled by HW ( and trigger a SRST/PoR/PS Error Out) or trigger an interrupt to PMC/PSM.

Error Management in PLM

The PLM Error Manager provides APIs for assigning a default error action for errors present in PMC and PSM in response to an error. During initialization of the PLM modules, the PLMI initializes the Error Manager, enables errors, and sets error action for each error in accordance with the Error Table structure defined in the xplmi_err.c file.

Following are the error actions supported by PLM for each error in PMC and PSM:

  1. POR - Power On Reset

  2. SRST - System restart

  3. CUSTOM (Not supported through CDO)

  4. PS Error Out - Error Out

  5. Subsystem Shutdown - Shutdown of a specific subsystem

  6. Subsystem Restart - Restart of a specific subsystem

  7. No Action

  8. Register notifier - Notifying a specified subsystem when error occurs

Error Management CDO commands

The following CDO commands are supported by the PLM error management module.

Set Em Action

Command: Set EM Action

Reserved[31:25]=0

Security Flag[24]

Length[23:16]=3

EM=8

CMD_SET_EM_ACTION=1

Error Event ID

Reserved

Action

Error Mask

This command is used to set error action for the specified Error Event ID and Error Mask. Refer to xil_error_node.h file for the list of Error Event IDs supported and Error Masks supported. Currently error management APIs are not supported over IPI.

Actions:

  • Invalid – 0x0

  • Power On Reset  – 0x1

  • System Reset – 0x2

  • Custom Action – 0x3 (Not supported)

  • Error Out – 0x4

  • Subsystem Shutdown – 0x5

  • Subsystem Restart – 0x6

  • None – 0x7. Disable all actions on the Event and clear error status

Note: For PSM error events, the command returns failure if LPD is not initialized.

Register Notifier for EM Events

Command: Register Notifier

Reserved[31:24]=0

Length[23:16]=4

PMC_LIBPM=2

CMD_PM_REGISTER_NOTIFIER=5

Node ID (Error Event ID)

Event Mask (Error Mask)

Argument 1

Argument 2

EM supports notifying a subsystem when registered error occurs, using the register notifier API supported by XilPM. Use this command to register for notifications when registered errors occur. Refer to xil_error_node.h for a list of supported error event IDs and error masks.

  • Node ID: Can either be a Device ID or Error Event ID. Use an Error Event ID for registering error events.

  • Event Mask

    • For Device ID: Event Type

    • For Error Event ID: Error Mask

  • Argument 1

    • For Device ID: Wake

  • Argument 2

    • For Device ID: Enable

The register notifier for an event of an error event ID enables the error event by clearing the corresponding PMC/PSM_ERR#N_STATUS bit and writes to the corresponding PMC/PSM_IRQ#N_EN. The notifier returns an event index (which is a bit that notify callback sets) to indicate the occurrence of the event.

The register notifier command works with the notify callback command. With register notifier command, multiple subscribers (A72, R5) can register for a single error event notification.

For example, register notifier of error node GT_CR error event clears PMC_ERR1_STATUS.GT_CR, enables PMC_IRQ1_EN.GT_CR, and returns a number, for example, 5. Notify callback sets bit 5 of the event status to indicate that the GT_CR error has occurred.

 

Notify Callback

Command: Notify Callback

Reserved[31:24]=0

Length[23:16]=4

PMC_LIBPM=2

CMD_PM_NOTIFY_CALLBACK

Node ID (Error Event ID)

Event Status (Error Mask)

On notify callback of an event of Error Event ID, the Error Node is disabled. For example, notification of the Error Node GT_CR error event disables the error by writing to PMC_IRQ1_DIS.GT_CR. You must re-register to be notified again.

For more information of registration/un-registration of error events, see Event Management Framework section in UG1304.

PSM errors handling by PLM

The HW error actions supported by PMC EAM for PMC errors are SRST, POR, IRQ (Interrupt to PMC Microblaze) and Error Out. And the HW error actions supported by PSM EAM for PSM errors are PSM_CR (PSM errors routed to PMC Microblaze as PSM_CR), PSM_NCR (PSM errors routed to PMC Microblaze as PSM_NCR), IRQ (Interrupt to PSM Microblaze) and SRST.

Even though these are the HW error actions, PLM supports the error actions mentioned in above section. So, any error can be configured to have the error action supported by PLM. Please refer to Additional information column in the table below to know the restrictions on the error actions for any error.

Since all the PLM supported error actions cannot be handled by the PSM HW supported error actions, the PSM errors are routed to PMC Microblaze either as PSM_CR or as PSM_NCR. So, all the PSM EAM errors are handled by PLM only. If a user selected error action for any PSM error matches with the PSM_CR error action, then PLM configures that PSM error as PSM_CR. If the user selected error action doesn’t match with PSM_CR error action, then PLM configures that as PSM_NCR and PLM executes the configured error action.

Note: Error action configuration for PSM errors is allowed only when LPD is initialized. If LPD is uninitialized, the PSM errors cannot be configured or handled

SW errors

The SW errors are the extended feature of the PLM error management. User can add any error to the SW errors list. These can also be configured through EAM CDO command. All the error actions are supported and handled by PLM. For the SW error to be handled by PLM, “XPlmi_HandleSwError" API need to be called from SW whenever there is an error occurrence.

For example. the “PLM_EXCEPTION” is not in the PMC EAM errors. So, to have any error action when any exception occurs, this is listed as one of the SW errors in the ErrorTable. And in the PLM Exception Handler, PLM calls “XPlmi_HandleSwError" to execute the configured error action. Please refer to https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_apps/versal_plm/src/common/xplm_proc.c#L115 code for the same. Also, please refer to xil_error_node.h for the Error Node ID for SW errors and the list of SW errors.

EAM errors and their default error actions

Below table lists PMC, PSM and SW supported errors and their default error actions set by PLM. Please refer to ErrorTable in xplmi_err.c file for the same.

Error IDs

Error

Description

Default action

(In 2022.1)

Default action

(In 2022.2)

Additional information

Error IDs

Error

Description

Default action

(In 2022.1)

Default action

(In 2022.2)

Additional information

PMC Error1

0x0

BOOT_CR

PMC Boot Correctable Error. (Set by ROM code during ROM execution during Boot)

No action

Preferred action: None

 

0x1

BOOT_NCR

PMC Boot Non-Correctable Error. (Set by ROM code during ROM execution during Boot)

No action

Preferred action: None

 

0x2

FW_CR

PMC Firmware Boot Correctable Error. (Set by PLM during firmware execution during Boot)

Error Out

Error Out

 

0x3

FW_NCR

PMC Firmware Boot Non-Correctable Error. (Set by PLM during firmware execution during Boot)

SRST

SRST

 

0x4

GSW_CR

General Software Correctable Error. (Set by any processors after Boot)

No action

Default to PLM Print Log

 

0x5

GSW_NCR

General Software Non-Correctable Error. (Set by any processors after Boot)

No action

Default to PLM Print Log

 

0x6

CFU

CFU Error

No action

None

 

0x7

CFRAME

CFRAME Error

No action

None

 

0x8

PSM_CR

PSM Correctable Error (Summary from PSM Error Management).

SRST

SRST

The default error action for PSM_CR is SRST. PLM allows changing the error action for this error only once. If user tries to change it, PLM gives “XPLMI_CANNOT_CHANGE_ACTION" minor error as response. And the allowed error actions are HW (SRST, POR and Error Out) error actions only. If other error action is specified, PLM gives “XPLMI_INVALID_ERROR_ACTION" minor error as response.

0x9

PSM_NCR

PSM Non-Correctable Error (Summary from PSM Error Management).

CUSTOM

CUSTOM

PLM doesn’t allow changing the error action for PSM_NCR through a CDO. If user tries to change it, PLM gives “XPLMI_CANNOT_CHANGE_ACTION" minor error as response.

0xA

DDRMC_MB_CR

DDRMC MB Correctable ECC Error.

No action

Default to PLM Print Log

 

0xB

DDRMC_MB_NCR

DDRMC MB Non-Correctable ECC Error.

No action

Default to PLM Print Log

 

0xC

NOC_TYPE1_CR

NoC Type1 Correctable Error.

No action

Default to PLM Print Log

 

0xD

NOC_TYPE1_NCR

NoC Type1 Non-Correctable Error.

No action

Default to PLM Print Log

 

0xE

NOC_USER

NoC User Error.

No action

None

 

0xF

MMCM

MMCM Lock Error. (PLL for PL)

No action

Default to PLM Print Log

 

0x10

ME_CR

ME Correctable Error.

No action

None

 

0x11

ME_NCR

ME Non-Correctable Error.

No action

Default to PLM Print Log

 

0x12

DDRMC_MC_CR

DDRMC MC Correctable ECC Error.

No action

Default to PLM Print Log

 

0x13

DDRMC_MC_NCR

DDRMC MC Non-Correctable ECC Error.

No action

Default to PLM Print Log

 

0x14

GT_CR

GT Correctable Error.

No action

None - This error is not set to "PLM Print Log" because of SV60 VDU interrupts (scan clear and memclear done) are getting set and routed by default

 

0x15

GT_NCR

GT Non-Correctable Error.

No action

None - This error is not set to "PLM Print Log" because of SV60 VDU interrupts (scan clear and memclear done) are getting set and routed by default

 

0x16

PL_SMON_CR

PL Sysmon Correctable Error.

No action

Default to PLM Print Log

 

0x17

PL_SMON_NCR

PL Sysmon Non-Correctable Error.

No action

Default to PLM Print Log

 

0x18

PL0

User defined PL generic error.

No action

Preferred action: None

 

0x19

PL1

User defined PL generic error.

No action

Preferred action: None

 

0x1A

PL2

User defined PL generic error.

No action

Preferred action: None

 

0x1B

PL3

User defined PL generic error.

No action

Preferred action: None

 

0x1C

NPI_ROOT

NPI Root Error.

No action

None (Need to check later)

 

0x1D

SSIT_ERR3

SSIT Error from Slave SLR1. (Only used in Master SLR)

No action

Preferred action: None

 

0x1E

SSIT_ERR4

SSIT Error from Slave SLR2. (Only used in Master SLR)

No action

Preferred action: None

 

0x1F

SSIT_ERR5

SSIT Error from Slave SLR3. (Only used in Master SLR)

No action

Preferred action: None

 

PMC Error2

0x20

PMC_APB

General purpose PMC error, can be triggered by any of the following peripherals:

  • PMC Global Regsiters

  • PMC Clock & Reset (CRP)

  • PMC IOU Secure SLCR

  • PMC IOU SLCR

  • BBRAM Controller

  • PMC Analog Control Registers

  • RTC Control Registers

No action

Currently, this is being used for triggering secure lockdown to PLM by ROM. Default action is CUSTOM

 

0x21

PMC_ROM

PMC ROM Validation Error.

No action

Preferred action: None

 

0x22

MB_FATAL0

PMC PPU0 MB TMR Fatal Error.

No action

Default to PLM Print Log

 

0x23

MB_FATAL1

PMC PPU1 MB TMR Fatal Error.

No action

Default to PLM Print Log

 

0x24

PMC_PAR

PMC Switch and PMC IOU Parity Errors.

No action

Default to PLM Print Log

 

0x25

PMC_CR

PMC Correctable Errors:
PPU0 RAM correctable error.
PPU1 instruction RAM correctable error.
PPU1 data RAM correctable error.

No action

Default to PLM Print Log

 

0x26

PMC_NCR

PMC Non-Correctable Errors:
PPU0 RAM non-correctable error.
PPU1 instruction RAM non-correctable error.
PPU1 data RAM non-correctable error.
PRAM non-correctable error.

No action

Default to PLM Print Log

 

0x27

PMC_SMON0

PMC Temperature Shutdown Alert and Power Supply Failure Detection Errors from PMC Sysmon alarm[0]. (Indicates an alarm condition on any of SUPPLY0 to SUPPLY31)

No action

Default to PLM Print Log

 

0x28

PMC_SMON1

PMC Temperature Shutdown Alert and Power Supply Failure Detection Errors from PMC Sysmon alarm[1]. (Indicates an alarm condition on any of SUPPLY32 to SUPPLY63)

No action

Default to PLM Print Log

 

0x29

PMC_SMON2

PMC Temperature Shutdown Alert and Power Supply Failure Detection Errors from PMC Sysmon alarm[2]. (Indicates an alarm condition on any of SUPPLY64 to SUPPLY95)

No action

Default to PLM Print Log

 

0x2A

PMC_SMON3

PMC Temperature Shutdown Alert and Power Supply Failure Detection Errors from PMC Sysmon alarm[3]. (Indicates an alarm condition on any of SUPPLY96 to SUPPLY127)

No action

Default to PLM Print Log

 

0x2B

PMC_SMON4

PMC Temperature Shutdown Alert and Power Supply Failure Detection Errors from PMC Sysmon alarm[4]. (Indicates an alarm condition on any of SUPPLY128 to SUPPLY159)

No action

Default to PLM Print Log

 

0x2F

PMC_SMON8

PMC Temperature Shutdown Alert and Power Supply Failure Detection Errors from PMC Sysmon alarm[8]. (Indicates an over-temperature alarm)

Default action through PMC_DATA.CDO is SRST

Default to PLM Print Log

Action through CDO is SRST

 

0x30

PMC_SMON9

PMC Temperature Shutdown Alert and Power Supply Failure Detection Errors from PMC Sysmon alarm[9]. (Indicates a device temperature alarm)

No action

Default to PLM Print Log

 

0x31

CFI

CFI Non-Correctable Error.

No action

None as we are checking after PDI load

 

0x32

CFRAME_SEU_CRC

CFRAME SEU CRC Error.

No action

Preferred action: None as this error is getting routed to IOMODULE as well and XilSem is handling them. Additionally, XilSem is planning to add SW errors through which this error occurrence is communicated to user based on error action configured

 

0x33

CFRAME_SEU_ECC

CFRAME SEU ECC Error.

No action

Preferred action: None as this error is getting routed to IOMODULE as well and XilSem is handling them. Additionally, XilSem is planning to add SW errors through which this error occurrence is communicated to user based on error action configured

 

0x36

RTC_ALARM

RTC Alarm Error.

No action

Preferred action: None

 

0x37

NPLL

PMC NPLL Lock Error (This error can be unmasked after the NPLL is locked to alert when the NPLL loses lock).

No action

Preferred action: None

 

0x38

PPLL

PMC PPLL Lock Error (This error can be unmasked after the PPLL is locked to alert when the PPLL loses lock).

No action

Preferred action: None

 

0x39

CLK_MON

Clock Monitor Errors.
Collected from CRP's CLKMON_STATUS register.

No action

Default to PLM Print Log

 

0x3A

PMC_TO

PMC Interconnect Timeout Errors.
Collected from:
Interconnect mission interrupt status register.
Interconnect latent status register.
Timeout interrupt status register for SERBs.

No action

Default to PLM Print Log

 

0x3B

PMC_XMPU

PMC XMPU Errors:
Register access error on APB.
Read permission violation.
Write permission violation.
Security violation.

CUSTOM

CUSTOM

 

0x3C

PMC_XPPU

PMC XPPU Errors:
Register access error on APB.
Master ID not found.
Read permission violation.
Master ID parity error.
Master ID access violation.
TrustZone violation.
Aperture parity error.

CUSTOM

CUSTOM

 

0x3D

SSIT_ERR0

For Master SLR: SSIT Error from Slave SLR1.
For Slave SLRs: SSIT Error0 from Master SLR.

No action

CUSTOM for SSIT devices

 

0x3E

SSIT_ERR1

For Master SLR: SSIT Error from Slave SLR2.
For Slave SLRs: SSIT Error1 from Master SLR.

No action

CUSTOM for SSIT devices

 

0x3F

SSIT_ERR2

For Master SLR: SSIT Error from Slave SLR3.
For Slave SLRs: SSIT Error2 from Master SLR.

No action

CUSTOM for SSIT devices

 

PSM Error1

0x40

PS_SW_CR

PS Software can write to trigger register to generate this Correctable Error.

No action

Default to PLM Print Log

 

0x41

PS_SW_NCR

PS Software can write to trigger register to generate this Non-Correctable Error.

No action

Default to PLM Print Log

 

0x42

PSM_B_CR

PSM Firmware can write to trigger register to generate this Correctable Error.

No action

Default to PLM Print Log

 

0x43

PSM_B_NCR

PSM Firmware can write to trigger register to generate this Non-Correctable Error.

No action

Default to PLM Print Log

 

0x44

MB_FATAL

Or of MB Fatal1, Fatal2, Fatal3 Error.

No action

Default to PLM Print Log

 

0x45

PSM_CR

PSM Correctable

No action

Default to PLM Print Log

 

0x46

PSM_NCR

PSM Non-Correctable

No action

Default to PLM Print Log

 

0x47

OCM_ECC

Non-Correctable ECC Error during an OCM access.

No action

Default to PLM Print Log

 

0x48

L2_ECC

Non-Correctable ECC Error during APU L2 Cache access.

No action

Default to PLM Print Log

 

0x49

RPU

ECC Errors during a RPU memory access. Floating-point operation exceptions. RPU REG APB error.

No action

Default to PLM Print Log

 

0x4A

RPU_LS

RPU Lockstep Errors from R5_0. The Lockstep error is not initialized until RPU clock is enabled; therefore, error outcomes are masked by default and are expected to be unmasked after processor clock is enabled and before its reset is released.

No action

Default to PLM Print Log

 

0x4B

RPU_CCF

RPU Common Cause Failures ORed together. The CCF Error register with the masking capability has to reside in the RPU.

No action

Default to PLM Print Log

 

0x4C

GIC_AXI

APU GIC AXI Error by the AXI4 master port, such as SLVERR or DECERR.

No action

Default to PLM Print Log

 

0x4D

GIC_ECC

APU GIC ECC Error, a Non-Correctable ECC error occurred in any ECC-protected RAM.

No action

Default to PLM Print Log

 

0x4E

APLL_LOCK

APLL Lock Errors. The error can be unmasked after the PLL is locked to alert when the PLL loses lock.

No action

Preferred action: None

 

0x4F

RPLL_LOCK

RPLL Lock Errors. The error can be unmasked after the PLL is locked to alert when the PLL loses lock.

No action

Preferred action: None

 

0x50

CPM_CR

CPM Correctable Error.

No action

Default to PLM Print Log

 

0x51

CPM_NCR

CPM Non-Correctable Error.

CUSTOM

CUSTOM

 

0x52

LPD_APB

LPD APB Errors from:
IPI REG
USB2 REG
CRL REG
LPD AFIFM4 REG
LPD IOU REG
LPD IOU SECURE SLCR REG
LPD SLCR REG
LPD SLCR SECURE REG

No action

Default to PLM Print Log

 

0x53

FPD_APB

FPD APB Errors from:
FPD AFIFM0 REG
FPD AFIFM2 REG
FPD SLCR REG
FPD SLCR SECURE REG
CRF REG

No action

Default to PLM Print Log

 

0x54

LPD_PAR

Data parity errors from the interfaces connected to the LPD interconnect.

No action

Default to PLM Print Log

 

0x55

FPD_PAR

Data parity errors from the interfaces connected to the FPD interconnect.

No action

Default to PLM Print Log

 

0x56

IOU_PAR

LPD IO Peripheral Unit Parity Error.

No action

Default to PLM Print Log

 

0x57

PSM_PAR

Data parity errors from the interfaces connected to the PSM interconnect.

No action

Default to PLM Print Log

 

0x58

LPD_TO

LPD Interconnect Timeout errors.
Collected from:
Timeout errors at the slaves connected to the LPD interconnect.
Address decode error.
Interconnect mission errors for the slaves connected to the LPD interconnect.

No action

Default to PLM Print Log

 

0x59

FPD_TO

FPD Interconnect Timeout errors.
Collected from:
Coresight debug trace alarms.
Timeout errors at the slaves connected to the FPD interconnect.
Address decode error.
Data parity errors on the interfaces connected to the FPD interconnect.

No action

Default to PLM Print Log

 

0x5A

PSM_TO

PSM Interconnect Timeout Errors.
Collected from:
Interconnect mission errors for PSM_LOCAL slave or PSM_GLOBAL slave or MDM slave or LPD interconnect or PSM master.
Interconnect latent errors for PSM_LOCAL slave or PSM_GLOBAL slave or MDM slave or LPD interconnect or PSM master.
Timeout errors at the slaves connected to the PSM interconnect.

No action

Default to PLM Print Log

 

0x5B

XRAM_CR

XRAM Correctable error. (Only applicable in devices that have XRAM)

No action

Default to PLM Print Log

 

0x5C

XRAM_NCR

XRAM Non-Correctable error. (Only applicable in devices that have XRAM)

No action

Default to PLM Print Log

 

PSM Error2

0x60

LPD_SWDT

Error from Watchdog Timer in the LPD Subsystem.

No action

Default to PLM Print Log

 

0x61

FPD_SWDT

Error from Watchdog Timer in the FPD Subsystem.

No action

Default to PLM Print Log

 

0x72

LPD_XMPU

LPD XMPU Errors:
Register access error on APB.
Read permission violation.
Write permission violation.
Security violation.

CUSTOM

CUSTOM

 

0x73

LPD_XPPU

LPD XPPU Errors:
Register access error on APB.
Master ID not found.
Read permission violation.
Master ID parity error.
Master ID access violation.
TrustZone violation.
Aperture parity error.

CUSTOM

CUSTOM

 

0x74

FPD_XMPU

FPD XMPU Errors:
Register access error on APB.
Read permission violation.
Write permission violation.
Security violation.

CUSTOM

CUSTOM

 

SW Errors

0x80

HB_MON_0

Health Boot Monitoring Error0

No action

As per SW configuration

 

0x81

HB_MON_1

Health Boot Monitoring Error1

No action

As per SW configuration

 

0x82

HB_MON_2

Health Boot Monitoring Error2

No action

As per SW configuration

 

0x83

HB_MON_3

Health Boot Monitoring Error3

No action

As per SW configuration

 

0x84

PLM_EXCEPTION

PLM Exception during run time

No action

As per SW configuration

 

Configuration of EAM errors through a CDO

Since the tools support to configure the EAM errors is not yet added, this section describes how they can be configured through a CDO. Below snippet shows the example EAM CDO which can be modified as per the requirement, can be included in the BIF as a CDO and PDI can be generated.

Loader

PDI contains all the images that must be loaded into the system. PLM reads the PDI from the boot device and loads the images to the respective memories based on the image header. For more details on PDI, refer to UG1304.

Following are the responsibilities of XilLoader:

  • Boot device initialization

  • Interface for modules to load/start/look up the image present in PDI

  • Interface with XilPDI to decode and validate images present in PDI

  • Support secure boot loading using XilSecure module

  • Subsystem bring up by calling XilPM

Please refer to CDO spec for the list of CDO/IPI commands supported by XilLoader.

PM

Platform Management (XilPM) is a library that provides interfaces to create and manage subsystems, MIO, Clocks, Power and Reset settings of nodes. The following table provides the list of commands supported by this module. For details about Platform Management, refer to the Chapter 10: Versal ACAP Platform Management in UG1304

Secure

The XilSecure library is a library of security drivers that access the hardened cryptographic cores to support the AES-GCM 256-bit/128-bit engine, the RSA/ECC engine that supports RSA-4096, RSA-3076, RSA-2048 as well as ECDSA NIST P-384 and NIST P-521, and the SHA3/384 engine.
For more information, see Chapter 9: Security in UG1304.

Sem

The Xilinx Soft Error Mitigation (XilSEM) library is a pre-configured, pre-verified solution to detect and optionally correct soft errors in Configuration Memory of Versal ACAPs.
See the OS and Libraries Document Collection (UG643) for more information.

PLM Build Flags

The following table lists the important build flags in PLM and their usage. For a complete list of build flags, see the xplmi_config.h file in the XilPLMI library.

Flag

Description

Requires these flags/build options to be enabled

Default Setting

Flag

Description

Requires these flags/build options to be enabled

Default Setting

PLM_PRINT_NO_UART

Disables prints to UART. Prints to memory are still enabled as defined by PLM DEBUG macros below

None

Disabled

PLM_PRINT

Prints PLM header and any mandatory prints

None

Disabled

PLM_DEBUG

Prints basic information and any error messages

None

Enabled

PLM_DEBUG_INFO

Prints with format specifiers in addition to the basic information

None

Disabled

PLM_DEBUG_DETAILED

Prints detailed information

None

Disabled

PLM_PRINT_PERF

Prints the time taken for loading the partitions, images and tasks

Any of the above mentioned print related flags

Enabled

PLM_PRINT_PERF_POLL

Prints the time taken for any poll for the MASK_POLL command

PLM_PRINT_PERF

Disabled

PLM_PRINT_PERF_DMA

Prints the time taken for PMC DMA, QSPI and OSPI

PLM_PRINT_PERF

Disabled

PLM_PRINT_PERF_CDO_PROCESS

Prints the time taken for processing a CDO file

PLM_PRINT_PERF

Disabled

PLM_PRINT_PERF_KEYHOLE

Prints the time taken for processing keyhole command

PLM_PRINT_PERF

Disabled

PLM_PRINT_PERF_PL

Prints the PL power and house cleaning status

PLM_PRINT_PERF

Disabled

PLM_QSPI_EXCLUDE

Excludes QSPI code when this flag is enabled

None

Disabled

PLM_SD_EXCLUDE

Excludes SD code when this flag is enabled

None

Disabled

PLM_OSPI_EXCLUDE

Excludes OSPI code when this flag is enabled

None

Disabled

PLM_USB_EXCLUDE

Excludes USB code when this flag is enabled

None

Enabled

PLM_SEM_EXCLUDE

Excludes SEM module code when this flag is enabled

None

Disabled

PLM_SECURE_EXCLUDE

Excludes Secure code when this flag is enabled

None

Disabled

PLM_DEBUG_MODE

Changes the PLM to Debug mode to keep the system in hang state instead of doing SRST in case of an error for the user to debug further

None

Disabled

PLM_ENABLE_STL

Enables STL when this flag is enabled

Add STL library to the PLM BSP

Disabled

XILPM_USB_EXCLUDE

Excludes USB related code for the XilPM library

None

Disabled

PLM Feature Configuration

In Zynq UltraScale+, for applications FSBL and PMUFW changing of configuration (enable/disable certain feature(s)) was possible through Vitis GUI (where we can define or undefine), same could be done in command line using -D or -U as parameter to make (for defining or undefining). 

In Versal, most of the PLM application functionality is distributed to various libraries and configuration of various features is done in XilPLMI library. Hence, these features shall be enabled/disabled through Board Support Package Settings. This enhancement in PLM is done in 2022.1

Enabling of certain features (e.g. boot modes, SEM feature, UART debug) as referred here is w.r.t. enabling the corresponding support in PLM. For these features to be fully enabled and available, the hardware configuration(s) corresponding to these features too should be available. However, disabling these features in PLM results in overall disabling irrespective of the corresponding hardware configuration.

Below table lists the PLMI library configuration options, their description and default configuration:

Option Name

Description

Type/Options

Default Value

Option Name

Description

Type/Options

Default Value

plm_uart_dbg_en

Enables (if enabled in hardware design too) or Disables Debug prints from UART (log to memory done irrespectively)

Bool (true, false)

true

plm_dbg_lvl

Selects the debug logs level

Enum
(level0 for minimal, level1 for general, level2 for info, level3 for detailed)

level1

plm_mode

Selects between Release and Debug modes (PLM errors lead to SRST for former and system hang for latter)

Enum (release, debug)

release

plm_perf_en

Enables or Disables Boot time measurement

Bool (true, false)

true

plm_qspi_en

Enables (if enabled in hardware design too) or Disables QSPI boot mode

Bool (true, false)

true

plm_sd_en

Enables (if enabled in hardware design too) or Disables SD boot mode

Bool (true, false)

true

plm_ospi_en

Enables (if enabled in hardware design too) or Disables OSPI boot mode

Bool (true, false)

true

plm_sem_en

Enables (if enabled in hardware design too) or Disables SEM feature

Bool (true, false)

true

plm_secure_en

Enables or Disbales Secure features

Enables or Disbales Secure features

true

plm_usb_en

Enables (if enabled in hardware design too) or disables USB boot mode

Bool (true, false)

false

plm_nvm_en

Enables or Disables NVM handlers

Bool (true, false)

false

plm_puf_en

Enables or Disables PUF handlers

Bool (true, false)

false

plm_stl_en

Enables or Disables STL

Bool (true, false)

false

PLM Feature Configuration through Vitis GUI

  • Click on the <project>.prj file and click on the "Navigate to BSP Settings" button as shown in below screen.

  • Click on the Modify BSP Settings… button as shown in below screen.

  • All the configurable libraries will be shown with tick mark in the Supported Libraries frame.

  • Click on the xilplmi library in the GUI as shown in the below screen. All the configurable parameters for the library xilplmi are now visible under column "Name". By default "Value" and "Default" fields show same configuration.

  • Click on Value column against configurable to list the available options against configuration. Change the selection as appropriate and click on OK button. Wait until the BSP generation happens as per the selection.

  • Now build the PLM project as usual.

PLM Feature Configuration through xsct

The below snippet shows steps involved in initially building the PLM with default configuration, then changing the debug level to debug info and regenerate BSP and rebuilding PLM, and then finally changing the debug level back to general (which is default), enabling the USB boot mode and regenerate BSP and rebuilding PLM. Refer above table for the different configuration options.

PLM Feature Configuration for PetaLinux

Refer above table for the different configuration options. Below example shows how to enable USB boot mode (which is disabled by default). 

Create a _plm_ _bbappend_ file and add below content

To add BSP flags(to enable USB boot mode) in PLM:

Building PLM: 

PLM Foot Print

PPU RAM which is of 384KB is used for PLM elf (Text, Data, BSS and Stack sections). In this, 16KB of memory is reserved for user code to add any custom code to the PLM.

This section contains the approximate details of PLM memory footprint with various build flags enabled. Refer to PLM Build Flags section above for the list of build flags and their default settings.

In PLM, PLM_DEBUG and PLM_PRINT_PERF build flags along with all modules are enabled by default.

[2022.2]

S No.

 

Feature/Build Flag

Size occupied (KB)

Free space (KB)

Additional Notes

Remarks

S No.

 

Feature/Build Flag

Size occupied (KB)

Free space (KB)

Additional Notes

Remarks

1

PLM default build

363.6

20.4

Default PLM includes all PLM modules and basic PLM prints, and has time stamp enabled. (PLM_DEBUG and PLM_PRINT_PERF)

 

2

PLM_PRINT_NO_UART enabled/plm_uart_dbg_en set to false

363.6

20.4

Disables prints to UART (Print to memory is enabled irrespective of this option being set)

This estimate is with the combination of (1) and (2)

3

PLM_PRINT enabled/plm_dbg_lvl set to level 0

331.9

52.1

Enables only mandatory prints

This estimate is with PLM_PRINT macro enabled and all other print macros (PLM_DEBUG, PLM_DEBUG_INFO and PLM_DEBUG_DETAILED) disabled

4

PLM_DEBUG_INFO enabled/plm_dbg_lvl set to level 2

376.6

7.4

Enables more info prints

This estimate is with PLM_DEBUG_INFO macro enabled and all other print macros (PLM_PRINT, PLM_DEBUG and PLM_DEBUG_DETAILED) disabled

5

PLM_DEBUG_DETAILED enabled/plm_dbg_lvl set to level 3

Overflowed by 1480 bytes

-

Enables detailed debug prints

This estimate is with PLM_DEBUG_DETAILED macro enabled and all other print macros (PLM_PRINT, PLM_DEBUG and PLM_DEBUG_INFO) disabled

6

PLM_DEBUG_MODE enabled/plm_mode set to debug

362.8

21.2

PLM debug mode is enabled when PLM_DEBUG_MODE flag is enabled or plm_mode option is set to debug

This estimate is with the combination of (1) and (6)

7

PLM_PRINT_PERF disabled/plm_perf_en set to false

363.3

20.7

Disables PLM performance prints

This estimate is with the combination of (1) and (7)

8

PLM_QSPI_EXCLUDE enabled/plm_qspi_en set to false

355.5

28.5

Excludes QSPI related code

This estimate is with the combination of (1) and (8)

9

PLM_SD_EXCLUDE enabled/plm_sd_en set to false

343.3

40.7

Excludes SD related code

This estimate is with the combination of (1) and (9)

10

PLM_OSPI_EXCLUDE enabled/plm_ospi_en set to false

363.6

20.4

Excludes OSPI related code

This estimate is with the combination of (1) and (10)

11

PLM_SEM_EXCLUDE enabled/plm_sem_en set to false

363.6

20.4

Excludes SEM related code

This estimate is with the combination of (1) and (11)

12

PLM_SECURE_EXCLUDE enabled/plm_secure_en set to false

317.5

66.5

Excludes Secure related code

This estimate is with the combination of (1) and (12)

13

PLM_USB_EXCLUDE disabled/plm_usb_en set to true

374.1

9.9

Enables USB related code

This estimate is with the combination of (1) and (13)

14

PLM_NVM_EXCLUDE disabled/plm_nvm_en set to true

Overflowed by 232 bytes

-

Enables NVM related code

This estimate is with the combination of (1) and (14)

15

PLM_PUF_EXCLUDE disabled/plm_puf_en set to true

366.5

17.5

Enabled PUF related code

This estimate is with the combination of (1) and (15)

[2023.1]

S No.

Feature/Build Flag

Size occupied (KB)

Free space (KB)

Additional Notes

Remarks

1

PLM default build

376.35

7.65

Default PLM includes all PLM modules and basic PLM prints, and has time stamp enabled. (PLM_DEBUG and PLM_PRINT_PERF)

 

2

PLM_PRINT_NO_UART enabled/plm_uart_dbg_en set to false

376.35

7.65

Disables prints to UART (Print to memory is enabled irrespective of this option being set)

This estimate is with the combination of (1) and (2)

3

PLM_PRINT enabled/plm_dbg_lvl set to level 0

342.23

41.77

Enables only mandatory prints

This estimate is with PLM_PRINT macro enabled and all other print macros (PLM_DEBUG, PLM_DEBUG_INFO and PLM_DEBUG_DETAILED) disabled

4

PLM_DEBUG_INFO enabled/plm_dbg_lvl set to level 2

Overflowed by 7664 bytes

-

Enables more info prints

This estimate is with PLM_DEBUG_INFO macro enabled and all other print macros (PLM_PRINT, PLM_DEBUG and PLM_DEBUG_DETAILED) disabled

5

PLM_DEBUG_DETAILED enabled/plm_dbg_lvl set to level 3

Overflowed by 16880 bytes

-

Enables detailed debug prints

This estimate is with PLM_DEBUG_DETAILED macro enabled and all other print macros (PLM_PRINT, PLM_DEBUG and PLM_DEBUG_INFO) disabled

6

PLM_DEBUG_MODE enabled/plm_mode set to debug

374.46

9.54

PLM debug mode is enabled when PLM_DEBUG_MODE flag is enabled or plm_mode option is set to debug

This estimate is with the combination of (1) and (6)

7

PLM_PRINT_PERF disabled/plm_perf_en set to false

376.15

7.85

Disables PLM performance prints

This estimate is with the combination of (1) and (7)

8

PLM_QSPI_EXCLUDE enabled/plm_qspi_en set to false

367.21

16.79

Excludes QSPI related code

This estimate is with the combination of (1) and (8)

9

PLM_SD_EXCLUDE enabled/plm_sd_en set to false

353.46

30.54

Excludes SD related code

This estimate is with the combination of (1) and (9)

10

PLM_OSPI_EXCLUDE enabled/plm_ospi_en set to false

376.35

7.65

Excludes OSPI related code

This estimate is with the combination of (1) and (10)

11

PLM_SEM_EXCLUDE enabled/plm_sem_en set to false

376.35

7.65

Excludes SEM related code

This estimate is with the combination of (1) and (11)

12

PLM_SECURE_EXCLUDE enabled/plm_secure_en set to false

324.36

59.64

Excludes Secure related code

This estimate is with the combination of (1) and (12)

13

PLM_USB_EXCLUDE disabled/plm_usb_en set to true

Overflowed by 3088 bytes

-

Enables USB related code

This estimate is with the combination of (1) and (13)

14

PLM_NVM_EXCLUDE disabled/plm_nvm_en set to true

Overflowed by 12872 bytes

-

Enables NVM related code

This estimate is with the combination of (1) and (14)

15

PLM_PUF_EXCLUDE disabled/plm_puf_en set to true

378.89

5.11

Enabled PUF related code

This estimate is with the combination of (1) and (15)

16

PLM_ECDSA_EXCLUDE  enabled/plm_ecdsa_en set to false

361.5

22.5

Excludes ECDSA related code

This estimate is with the combination of (1) and (16)

17

PLM_RSA_EXCLUDE  enabled/plm_rsa_en set to false

368.5

15.5

Excludes RSA related code

This estimate is with the combination of (1) and (17)

18

PLM_ENABLE_PLM_TO_PLM_COMM disabled/ssit_plm_to_plm_comm_en set to false

376.35

7.65

Excludes PLM to PLM communication related code

This estimate is with the combination of (1) and (18)

Debugging Tips

PLM throws XYZ error code when any error occurs. This error code will also be stored in PMC_GLOBAL FW_ERR (0xF1120100) registers.

Reading PLM memory log and interpreting PLM prints

By default PLM prints are stored in PMC RAM at address 0xF2019000. Maximum size allocated for PLM print log memory is 16KB. After that PLM will overwrite the existing prints.

From xsdb, we can read and view the prints using either of the following three commands.

If prints are read using first command, user can open uart.bin in vi or any editor and see the prints.

Below is the example log for the PLM prints:

"[X]" at the start of the print signifies the total cumulative time taken in ms from the start of PLM to that print statement.

"X ms for Partition#: Y, Size: Z Bytes" - this print indicates time taken for loading partition number Y of size Z bytes is X ms.

ROM time is from start of ROM to PLM start point.

"[X] Total PLM Boot Time" indicates that the total PLM boot time in ms.

PLM error code format:

0xXXXX_YYYY is the error code format.

XXXX - Major error code - PLM/LOADER/XPLMI error codes as defined in xplmi_status.h file in XilPLMI library

YYYY - Minor error code - Libraries / Drivers error code as defined in corresponding modules.

Below table describes the major error code decoding for CDO Command failures(Supported from 2020.2):

Error Code

Description

Error Code

Description

0x2XYZ

0x2XYZ - 0x2 indicates failure in CDO command

0x2XYZ - 0xX  indicates command module.

            1 - PLM,

            2 -PM,

            3 - SEM,

            7 - Loader,

            8 - Error,

etc..

Please refer https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilplmi/src/common/xplmi_modules.h#L61 for module IDs supported by PLM

0x2XYZ - 0xYZ indicate handler ID of the CDO command. Handler IDs can be checked in CDO spec against the module

PLMI handlers: Please refer to https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilplmi/src/common/xplmi_generic.c#L1985 for handlers supported in PLMI (GENERIC) module.

Ex: 0x223E

0x223E - 0x2 indicates failure in CDO command

0x223E - 0x2  indicates command failed in PM Command.

0x223E - 0x3E indicate handler ID of the PM command which is PM_INIT_NODE.

YYYY

Minor error code - Libraries / Drivers error codes as defined in corresponding modules.

Refer “Error Codes” Section Below