Versal NoC and DDR MC Design Process Guide
- Deanna DeMarco (Unlicensed)
- William Cassells (Unlicensed)
- Michael McGuirk (Unlicensed)
Xilinx has organized Versal documentation around design processes to help users find content based on specific design needs. This Wiki augments this approach by directing NoC/DDR MC users to the relevant documents, tutorials, examples and blogs as their development progresses through the design processes.
Table of Contents
Introduction
The documents every Versal NoC and DDR MC user needs are:
UG1304 - Versal Adaptive SoC System Software Developers Guide
Answer Record 75764: Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller - IP Release Notes and Known Issues
System and Solution Planning
This user needs to understand how to set up a NoC and DDR MC design, define a traffic specification and memory requirements, and design for performance.
Related Links
Tutorial: Modules 1-5 of Introduction to NoC DDRMC Design Flow
CEDStore: Simulating with the CIPS Verification IP
Chapter 5: NoC Performance Tuning in PG313
Board System Design
This user needs to to pin plan the DDR MC interface, observe PCB layout guidelines and model the physical interface. This user also needs to bring up and debug the DDR MC interface.
Related Links
Tutorial: Obtaining and Verifying Versal Adaptive SoC Memory Pinouts
Tutorial: DDR4 and LPDDR4 Timing Models for Hyperlinx DDRx Wizard in Versal Adaptive SoCs
Pinout Rules in PG313
Answer Record 76059: Versal Adaptive SoC DDRMC - DDR4 and LPDDR4/x PCB Simulation Support
Appendix A: Memory Interface Debug in PG313
Chapter 7: Boot and Configuration and Chapter 8: Platform Loader and Manager in UG1304
This document lists PLM error codes
Blog: A Brief Overview of the Versal Boot Files summarizes these chapters
Hardware, IP and Platform Development
This user needs to know how to use Vivado to create an Adaptive SoC design. The modules in the Introduction to NoC DDRMC Design Flow walk through the basics of how to create a NoC and DDR MC design in IPI while the other resources show how to integrate with other IPs.
Related Links
Tutorial: Modules 1-5 of Introduction to NoC DDRMC Design Flow
Blog: Basic read/write to AXI BRAM from PS-APU through NoC in Versal
CEDStore: AXI DMA on VCK190
Tutorial: Versal Embedded Design, section on Versal Adaptive SoC CIPS and NoC (DDR) IP Core Configuration
CEDStore: VCK190/VMK190 Configurable Example Design in Vivado
CEDStore: Simulating with the CIPS Verification IP
Example: Versal Network on Chip/Multiple DDR Memory Controllers Tutorial
System Integration and Validation
This user brings together the Adaptive SoC hardware, board design and software and needs system level debug tools to diagnose and resolve performance and power issues.
Related Links
Tutorial: Versal Embedded Design, section on Debugging Using the Vitis Software Platform
Tutorial: Versal JTAG Boot Tutorial
Chapter 7: Boot and Configuration and Chapter 8: Platform Loader and Manager in UG1304
Blog: How to leverage Versal CIPS IP from MicroBlaze
This post shows how to route a configuration complete signal from the PMC to the PL.
Embedded Software Development
This user cares about system software interactions with the NoC and DDR MC. This typically occurs during error reporting and handling.
Related Links
AI Engine Development
This user tends not to care about the NoC and DDR MC.
Related Links
PG352: If the CIPS LPD NoC connects the RPU to the AIE, there are some interesting addressing and PS routing side effects to be aware of.
Other Resources
UG1037 - Vivado Design Suite: AXI Reference Guide
Chapter 6 provides good general guidance on how to optimize any AXI system.
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