Versal NoC and DDR MC Design Process Guide

Xilinx has organized Versal documentation around design processes to help users find content based on specific design needs. This Wiki augments this approach by directing NoC/DDR MC users to the relevant documents, tutorials, examples and blogs as their development progresses through the design processes.

Table of Contents


The documents every Versal NoC and DDR MC user needs are:

System and Solution Planning

This user needs to understand how to set up a NoC and DDR MC design, define a traffic specification and memory requirements, and design for performance.

Board System Design

This user needs to to pin plan the DDR MC interface, observe PCB layout guidelines and model the physical interface. This user also needs to bring up and debug the DDR MC interface.

Hardware, IP and Platform Development

This user needs to know how to use Vivado to create an Adaptive SoC design. The modules in the Introduction to NoC DDRMC Design Flow walk through the basics of how to create a NoC and DDR MC design in IPI while the other resources show how to integrate with other IPs.

System Integration and Validation

This user brings together the Adaptive SoC hardware, board design and software and needs system level debug tools to diagnose and resolve performance and power issues.

Embedded Software Development

This user cares about system software interactions with the NoC and DDR MC. This typically occurs during error reporting and handling.

AI Engine Development

This user tends not to care about the NoC and DDR MC.

Other Resources

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