Versal AI Core

Versal AI Core

This page provides a list of resources to help you get started using the Versal AI Core,  including pre-built images for Xilinx development boards, tutorials, and example designs. More detailed information can be found by following the links provided on this page. 

Whether you're an expert or novice user, the easiest way to get started with a Xilinx development board is to start with a pre-built Linux image for your board.  If you're new the Xilinx embedded design flow, the Embedded Design Tutorial is the recommended way to learn the tools and design flow.  To build a custom Linux image, it's recommended that you start with a Petalinux BSP for one of the Xilinx boards, and then customize the configuration to suit your needs.

Table of Contents

Pre-Built Release Images

The pre-built images referenced here are for the Xilinx development boards. These can be loaded on to SD Cards on the Xilinx development boards and you can boot Linux. The Pre-Built Releases Images page includes images  for Versal, Zynq UltraScale+ MPSoC, Zynq UltraScale+ RFSoC and Zynq-7000.

Evaluation Boards and BSP

PetaLinux Board Support Packages (BSP) and Reference Examples include pre-built boot loaders, system images and bitstreams. Built-in tools allow a single command to deploy and boot these elements to either physical hardware, or to the included full QEMU system emulator. With PetaLinux, developers can have their Xilinx-based hardware booted and running within about 5 minutes after installation; ready for application, library and driver development.

NOTE: The VCK190 is in early access with availability to qualified customers. 

Xilinx provides one development boards for the Versal AI Core devices. For more information, the links below take you back to board-specific pages at Xilinx Evaluation Boards

Each  board also comes with a PetaLinux BSP that includes an image, documentation to recreate that image and a design that can be used as a starting point for the hardware user. There is one BSP for each board above. They are called PetaLinux BSPs since the Xilinx PetaLInux tool is used to create these images. The links to them take you back to the PetaLinux Download page at Please note that you will need a login to download these files.

Embedded Design Tutorial (EDT)

The Embedded Design Tutorial provides an introduction to using the Xilinx® Vivado® Design Suite flow for using the Versal ACAP VC1902. The latest versions of the EDT use the Vitis™ Unified Software Platform.  

 Embedded Software Stack on a Versal AI Core

The following is an overview of the embedded software stack for a Versal AI Core.

For system start-up, a Versal™ device must successfully initialize, boot, and configure from a supported boot source.

The Versal™ ACAP has four key system start-up phases, that are independent of the selected boot mode, from boot through life-cycle management:

  • Phase 1: Pre-Boot (PMC hardware), Power-up and Reset
  • Phase 2: Boot Setup (RCU BootROM), Initialization and boot header processing
  • Phase 3: Load Platform (PPU PLM), Boot image processing and configuration
  • Phase 4: Post-Boot (PPU PLM), Platform management and monitoring services

The following sections provide a simplified overview the four phases.

Phase 1 (Pre-Boot) and 2 (Boot Setup) are handled by the Platform Management Controller and RCU BootROM. This goes through the power up sequence and start executing the code in the RCU BootROM. This will select the boot device and validate the boot header. The control is then passed to the PMC Platform Processing Unit (PPU) which loads the Platform Loader and Manager (PLM) code. 

For full details please see the Versal ACAP Technical Reference Manual and Versal ACAP System Software Developers Guide

PLM - Platform Management and Boot

During Phase 3 (Load Platform) the PPU executes the PLM software from the PPU RAM. The PLM reads the programmable device image and the boot mode properties are setup. The PLM software configures the peripherals, programmable logic, and processing system then completes the initial device boot. The PLM loads the applications and data for the Arm Cortex-A72 and Cortex-R5F processors to various memories specified by the ELF file. These memories include on-board DDR and internal memories, such as OCM and TCM. 

For Phase 4 (Post-Boot) the PLM continues to run until the next POR or system reset, and is responsible for post-boot platform management tasks. Post-boot services include DFX reconfiguration, power management, subsystem restart, error management, and safety and security services.

ARM Trusted Firmware

ARM Trusted Firmware (ATF) provides a reference to secure software for ARMv8-A architecture and it provides implementations of various interface standards like PSCI(Power State Coordination Interface) and Secure monitor code for interfacing to Normal world software. Xilinx ARM trusted firmware is based on arm trusted firmware at
Xilinx ARM Trusted Firmware tree will be released and available at

For more information, go to the ATF page. 


U-Boot, short for Universal Boot Loader, is an open source, primary boot loader used in embedded devices to boot the device's operating system kernel that is frequently used in the Linux community. Xilinx uses U-Boot as a second stage boot loader in the Versal ACAP devices. For more information about U-Boot visit their page at

For more information about U-Boot on Versal AI Core devices,  go to the U-Boot page on this wiki.

Hypervisor (Optional)

On the Versal AI Core devices, a hypervisor can be used to run more than one virtual machine. There are several hypervisors supported on the Versal AI Core devices. The list can be found on the  Embedded Software EcoSystem 

For more information regarding hypervisor uses on Versal AI Core, please see the Multi-OS Support (AMP & Hypervisor) page.


Since Linux is the primary OS that people start with on the Versal ACAP devices,  there is more information on it at the Linux page. This includes the two different build tools used to create customer distributions. Xilinx's PetaLinux and Yocto, an open source project that is part of the Linux Foundation. The Linux page also describes how to build your own Linux from the source,  and links to information about the Linux drivers that Xilinx provides. 


For full information on Versal ACAP technical details and software development please see the following two documents. 

The following link a list of Design Hubs (lists of related documentation) for development on Versal ACAP devices from

The Xilinx Community Forums are places to get answers to questions or search for solutions to problems using Xilinx devices.

The Xilinx Developer site showcases projects using Xilinx products.


The Xilinx tools provide all required tool chains to compile and link applications for Xilinx supported platforms, create and configure hardware designs, and create bitstreams.

Installing the Xilinx Tools