The Versal example design will show how to run AXI DMA standalone application example on VCK190 and intended to demonstrate the AXI DMA standalone driver which is available as part of the Xilinx Vivado and Vitis.
CIPS and DDR
Configurable example design showing CIPS IP and DDR connections, delivered via the CED Store for use within Vivado
Configurable example design showing simulating with the CIPS Verification IP, delivered via the CED Store for use within Vivado
This Blog entry is intended to illustrate how to access the AXI BRAM from the Versal™ Application processing Unit (APU) through the NoC
CIPS & MicroBlaze
This blog post shows how to leverage Versal CIPS IP from MicroBlaze
This blog entry will cover important information you should understand before designing with Memory Interfaces on Versal™ ACAP devices.
This example connects many different DDR devices simultaneously in one design to communicate to PS through NoC. It connects one DDR4 device and two interleaved LPDDR4 devices, which requires one NoC instance to configure the DDRMC for the DDR4 device and another NoC instance to configure the two interleaved DDRMCs for the two LPDDR4 devices.