Linux Versal EDAC Driver
Table of Contents
Overview
This documents provides driver details about the Xilinx DDR ECC controller driver used in Versal SOC.
Supporting Features
Xilinx Versal DDR ECC Controller supports
Single bit error detection and correction
Double bit error detection.
Interrupt support.
Error injection support for both single bit and double bit errors.
Missing features, Known Issues and Limitations
In 2020.2, we are not supporting the DTG flow to generate final dt node for EDAC.
Kernel Configurations
The following kernel configuration options should be enabled for compiling the Xilinx Versal EDAC driver.
CONFIG_EDAC=y
CONFIG_EDAC_VERSAL=y
Enable the "EDAC Debug" configuration under CONFIG_EDAC - This is required for error injection support.
CONFIG_EDAC_DEBUG=y
Device tree Node
memory-controller@f6150000 {
compatible = "xlnx,versal-ddrmc";
status = "okay";
reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
reg-names = "base", "noc";
interrupt-parent = <0x5>;
interrupts = <0 0x93 4>;
xlnx,mc-id = <0x0>;
}; |
Requirements
DDRMC with ECC enabled design
The controller supports LPDDR configurations with different bus widths, such as DDR4x72 , LP4 x40 and LP4 x24.
On vck190 we have 64 bit DDR but only 32 lines are connected in the current setup for LPDDR in vck190.
When ECC is enabled in LPDDR4 configurations and the memory is only 16 bits, the rest of the bits are used for ECC.
LP4x24 and DDR4x72 is there is vck190 and the same is tested. We do not have 40 line LPDDR connected in vck190 this is not
tested.
Mainline Status
Mainlined
Test Procedure
DT changes:
For 2020.2 release we are not supporting DTG flow, so user must enable the memory controller node in the DTS file based on the design.
in DTS file, whichever DDRMC controller(>=1) is enabled (DDRMC0-DDRMC4), change the status variable from "disabled" to "okay" in memory-controller node.
Kernel Boot log for EDAC driver
root@xilinx-vc-p-a2197-00-reva-x-prc-01:~# dmesg | grep "edac"
[ 1.648412] EDAC DEBUG: edac_mc_sysfs_init: device mc created
[ 2.702865] EDAC DEBUG: edac_mc_alloc: allocating 2392 bytes for mci data (1 ranks, 1 csrows/channels)
[ 2.702912] EDAC DEBUG: edac_mc_add_mc_with_groups:
[ 2.702945] EDAC DEBUG: edac_create_sysfs_mci_device: device mc0 created
[ 2.702975] EDAC MC0: Giving out device to module xlnx_edac controller xlnx_ddr_controller: DEV f6150000.memory-controller (INTERRUPT) |
To reserve the test memory location for error injection
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
reserved: buffer@0 {
reusable;
reg =<0x0 0x2002000 0x0 0x00100000>;
};
};
reserved-driver@0 {
compatible = "xlnx,reserved-memory";
memory-region = <&reserved>;
};
Test logs for CE and UE errors injection:
|
Change log
2024.1
None
e453068 - EDAC/versal: Fix the error injection
95c65a7 - EDAC/versal: Report the bit position of the error
eea40ba - EDAC/versal: Do not send the cumulative values
5af54f8 - EDAC/versal: Add a NULL check for the user passed values
2023.2
None
2023.1
None
2022.2
None
2022.1
ff817e4 - edac: xilinx: make event manager registration configurable
f179b8 - edac: xilinx: Fix kernel-doc for two functions
2021.2
7d8a993 - driver: edac: Use error events header file in xilinx ddrmc driver
2021.1
d2aa9a9 - Fix the error path
734c865 - Add support for registering for notification
d5a09f3 - enable the UE interrupt in IRQ1
2020.2
043c48a - New driver added
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