This wiki shows how to build a Versal application that does not require DDR.

Table of Contents

Introduction

A small footprint, bare-metal Versal application might not require DDR memory on the integrated memory controller (DDRMC). This page walks through a Vivado IP Integrator (IPI) block design and a Vitis bare-metal application without DDR. In this example, we will add a BRAM controller to the NoC and a BRAM controller to a CIPS master AXI port. We will use Vitis to write a bare-metal application to access the BRAM over the NoC and run code from the AXI BRAM.

Vivado IPI Design

We will start with a basic Vivado IPI Versal block design (BD) targeting the VCK190 board.

Create a Vivado project for your target board and create a Block Design (BD). The BD is going to look like Figure 1 when we are done.

Open

Figure 1. Versal Block Design

Add CIPS Block

1. Add a CIPS block from the catalog to your BD.

2. Run Block Automation.

3. Select All Automation and configure as shown in Figure 2.

   1. PL clocks = 1

   2. PL reset = 1

   3. Memory Controller = None

      Open

      

      Figure 2. CIPS Automation

Add the NoC IP

1. Add the AXI NoC from the catalog.

2. Run Block Automation.

3. Select All Automation and configure as shown in Figure 3.

   1. AXI BRAM Controller = 1.

   2. Memory Controller Type = None.

4. Run Connection Automation (accept defaults).

5. Run Connection Automation again (accept defaults).

Configure the CIPS IP

1. Double click on the CIPS block.

2. Click Next (accept defaults).

3. Click on PS PMC.

   1. Select PS PL Interfaces and enable the master AXI FPD bus as shown in Figure 4.

      1. Enable M_AXI_FPD

      2. Data Width = 128

4. Click on Finish, then Finish again.

5. Add a BRAM controller from the catalog and configure as shown in Figure 5.

   1. Check All Automation.

   2. Select S_AXI and select M_AXI_FPD as the Master Interface.

Configure the BRAM Controllers

1. Double click on both AXI BRAM Controller.

   1. Data Width = 128

2. Select the Address Editor tab.

   1. Click on the Expand All button.

   2. Set the desired Range (128KB in this example) for each segment as shown in Figure 6.

3. Click the Regenerate Layout button.

4. Save the project.

Build the Hardware

1. Create a HDL wrapper and let Vivado manage it.

2. Click Generate Device Image.

3. Export the hardware.

   1. File > Export > Export Hardware

   2. Click Next, click Next, Select “Include device image”, click Next and then click Finish

Vitis Software Design

1. Start an Application Project.

2. Create a new platform from hardware (XSA) and browse for the XSA we just exported from Vivado.

3. Create a “helloworld” application project.

4. Select the “Hello World” template.

5. Make sure that the BRAMs are mapped as expected in the Memory section in the “lscript.ld” file.

   MEMORY { versal_cips_0_pspmc_0_psv_pmc_ram_psv_pmc_ram : ORIGIN = 0xF2000000, LENGTH = 0x20000 versal_cips_0_pspmc_0_psv_r5_tcm_ram_global_psv_r5_tcm_ram_global : ORIGIN = 0xFFE00000, LENGTH = 0x40000 versal_cips_0_pspmc_0_psv_r5_1_atcm_global_psv_r5_1_atcm_global : ORIGIN = 0xFFE90000, LENGTH = 0x10000 versal_cips_0_pspmc_0_psv_r5_1_btcm_global_psv_r5_1_btcm_global : ORIGIN = 0xFFEB0000, LENGTH = 0x10000 versal_cips_0_pspmc_0_psv_ocm_ram_0_psv_ocm_ram_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000 axi_bram_ctrl_0 : ORIGIN = 0xA4000000, LENGTH = 0x100000 noc_bc : ORIGIN = 0x20100000000, LENGTH = 0x100000 }

6. Also in the “lscript.ld” file, map the logical sections to the appropriate memory regions.

   1. Remap all standard C sections into “versal_cips_0_pspmc_0_psv_ocm_ram_0_psv_ocm_ram_0” (OCM).

   2. Create the “.text.bram” section and map it to “axi_bram_ctrl_0”.

   3. Create the “.data.bram” section and map it to “noc_bc”.

      .text.bram : { . = ALIGN(64); *(.text_bram); } > axi_bram_ctrl_0 .data.bram : { . = ALIGN(64); *(.data_bram); } > noc_bc

7. Edit “platform.c”

   1. Include the “xil_mmu.h” header.

      #include "xil_mmu.h"

   2. Create an “update_pte” function to modify the page table entries for both BRAMs. We will mark these pages as normal, write-back, inner shareable cache.

   3. Call “update_pte” before exiting “init_platform”.

5. Edit “helloworld.c” and make the changes shown below.

6. Build the project.

7. Debug/Run the application.