Table of Contents
The Quad-SPI flash controller is part of the input/output peripherals (IOP) located within the processing system (PS). It is used to access multi-bit serial flash memory devices for high throughput and low pin count applications. The controller operates in one of three modes: I/O mode, linear addressing mode, and legacy SPI mode.
In I/O mode, software interacts closely with the flash device protocol. The software writes the flash commands and data to the controller using the four TXD registers. Software reads the RXD register that contains the data received from the flash device.
Linear Addressing Mode:
Linear addressing mode uses a subset of device operations to eliminate the software overhead that the I/O mode requires to read the flash memory. Linear Mode engages hardware to issue commands to the flash memory and control the flow of data from the flash memory bus to the AXI interface. The controller responds to memory requests on the AXI interface as if the flash memory were a ROM memory.
In legacy mode, QSPI controller acts as a normal SPI controller.
For Zynq QSPI:
- 32-bit AXI interface for Linear Addressing mode transfers
- 32-bit APB interface for I/O mode transfers
- Programmable bus protocol for flash memories from Micron and Spansion
- Legacy SPI and scalable performance: 1x, 2x, 4x, 8x I/O widths
- Flexible I/O
- Single SS 4-bit I/O flash interface mode
- Dual SS 8-bit parallel I/O flash interface mode
- Dual SS 4-bit stacked I/O flash interface mode
- Single SS, legacy SPI interface
- 16 MB addressing per device (32 MB for two devices)
For ZynqMP QSPI:
- Low-level (generic) access
- 3, 4, 6,…n-byte addresses
- SPI NAND flash devices
- Command queuing (generic FIFO depth is 32)'
- 4- or 8-bit interface
- Two chip-selected lines
- 4-bit bidirectional I/O signals
- x1, x2, and x4 read/write
- 44-bit address space on AXI in DMA mode
- Byte stripe when two data buses are connected
- Single interrupt for Quad-SPI/DMA interrupt status